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/*

 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and

 *                VA Linux Systems Inc., Fremont, California.

 *

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining

 * a copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation on the rights to use, copy, modify, merge,

 * publish, distribute, sublicense, and/or sell copies of the Software,

 * and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial

 * portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR

 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 *

 * Authors:

 *   Kevin E. Martin <martin@xfree86.org>

 *   Rickard E. Faith <faith@valinux.com>

 *   Alan Hourihane <alanh@fairlite.demon.co.uk>

 *

 * References:

 *

 * !!!! FIXME !!!!

 *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical

 *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April

 *   1999.

 *

 * !!!! FIXME !!!!

 *   RAGE 128 Software Development Manual (Technical Reference Manual P/N

 *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.

 *

 * !!!! FIXME !!!!  NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h

 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT

 * ON THE RADEON.  A FULL AUDIT OF THIS CODE IS NEEDED!

 */

#define BIOS8(r, o)  ((uchar) (r->bios[o]))

#define BIOS16(r, o) ((ushort)(r->bios[o] | (r->bios[(o) + 1] << 8)))

#define BIOS32(r, o) ((ulong) (r->bios[o] | (r->bios[(o) + 1] << 8) | \

	(r->bios[(o) + 2] << 16) | (r->bios[(o) + 3] << 24)))

enum {

	BIOS_START	= 0x48,

};

/* Registers for 2D/Video/Overlay */

#define ADAPTER_ID                   0x0f2c /* PCI */

#define AGP_BASE                     0x0170

#define AGP_CNTL                     0x0174

#       define AGP_APER_SIZE_256MB   (0x00 << 0)

#       define AGP_APER_SIZE_128MB   (0x20 << 0)

#       define AGP_APER_SIZE_64MB    (0x30 << 0)

#       define AGP_APER_SIZE_32MB    (0x38 << 0)

#       define AGP_APER_SIZE_16MB    (0x3c << 0)

#       define AGP_APER_SIZE_8MB     (0x3e << 0)

#       define AGP_APER_SIZE_4MB     (0x3f << 0)

#       define AGP_APER_SIZE_MASK    (0x3f << 0)

#define AGP_COMMAND                  0x0f60 /* PCI */

#define AGP_PLL_CNTL                 0x000b /* PLL */

#define AGP_STATUS                   0x0f5c /* PCI */

#       define AGP_1X_MODE           0x01

#       define AGP_2X_MODE           0x02

#       define AGP_4X_MODE           0x04

#       define AGP_FW_MODE           0x10

#       define AGP_MODE_MASK         0x17

#define ATTRDR                       0x03c1 /* VGA */

#define ATTRDW                       0x03c0 /* VGA */

#define ATTRX                        0x03c0 /* VGA */

#define AUX_SC_CNTL                  0x1660

#       define AUX1_SC_EN            (1 << 0)

#       define AUX1_SC_MODE_OR       (0 << 1)

#       define AUX1_SC_MODE_NAND     (1 << 1)

#       define AUX2_SC_EN            (1 << 2)

#       define AUX2_SC_MODE_OR       (0 << 3)

#       define AUX2_SC_MODE_NAND     (1 << 3)

#       define AUX3_SC_EN            (1 << 4)

#       define AUX3_SC_MODE_OR       (0 << 5)

#       define AUX3_SC_MODE_NAND     (1 << 5)

#define AUX1_SC_BOTTOM               0x1670

#define AUX1_SC_LEFT                 0x1664

#define AUX1_SC_RIGHT                0x1668

#define AUX1_SC_TOP                  0x166c

#define AUX2_SC_BOTTOM               0x1680

#define AUX2_SC_LEFT                 0x1674

#define AUX2_SC_RIGHT                0x1678

#define AUX2_SC_TOP                  0x167c

#define AUX3_SC_BOTTOM               0x1690

#define AUX3_SC_LEFT                 0x1684

#define AUX3_SC_RIGHT                0x1688

#define AUX3_SC_TOP                  0x168c

#define AUX_WINDOW_HORZ_CNTL         0x02d8

#define AUX_WINDOW_VERT_CNTL         0x02dc

#define BASE_CODE                    0x0f0b

#define BIOS_0_SCRATCH               0x0010

#define BIOS_1_SCRATCH               0x0014

#define BIOS_2_SCRATCH               0x0018

#define BIOS_3_SCRATCH               0x001c

#define BIOS_4_SCRATCH               0x0020

#define BIOS_5_SCRATCH               0x0024

#define BIOS_6_SCRATCH               0x0028

#define BIOS_7_SCRATCH               0x002c

#define BIOS_ROM                     0x0f30 /* PCI */

#define BIST                         0x0f0f /* PCI */

#define BRUSH_DATA0                  0x1480

#define BRUSH_DATA1                  0x1484

#define BRUSH_DATA10                 0x14a8

#define BRUSH_DATA11                 0x14ac

#define BRUSH_DATA12                 0x14b0

#define BRUSH_DATA13                 0x14b4

#define BRUSH_DATA14                 0x14b8

#define BRUSH_DATA15                 0x14bc

#define BRUSH_DATA16                 0x14c0

#define BRUSH_DATA17                 0x14c4

#define BRUSH_DATA18                 0x14c8

#define BRUSH_DATA19                 0x14cc

#define BRUSH_DATA2                  0x1488

#define BRUSH_DATA20                 0x14d0

#define BRUSH_DATA21                 0x14d4

#define BRUSH_DATA22                 0x14d8

#define BRUSH_DATA23                 0x14dc

#define BRUSH_DATA24                 0x14e0

#define BRUSH_DATA25                 0x14e4

#define BRUSH_DATA26                 0x14e8

#define BRUSH_DATA27                 0x14ec

#define BRUSH_DATA28                 0x14f0

#define BRUSH_DATA29                 0x14f4

#define BRUSH_DATA3                  0x148c

#define BRUSH_DATA30                 0x14f8

#define BRUSH_DATA31                 0x14fc

#define BRUSH_DATA32                 0x1500

#define BRUSH_DATA33                 0x1504

#define BRUSH_DATA34                 0x1508

#define BRUSH_DATA35                 0x150c

#define BRUSH_DATA36                 0x1510

#define BRUSH_DATA37                 0x1514

#define BRUSH_DATA38                 0x1518

#define BRUSH_DATA39                 0x151c

#define BRUSH_DATA4                  0x1490

#define BRUSH_DATA40                 0x1520

#define BRUSH_DATA41                 0x1524

#define BRUSH_DATA42                 0x1528

#define BRUSH_DATA43                 0x152c

#define BRUSH_DATA44                 0x1530

#define BRUSH_DATA45                 0x1534

#define BRUSH_DATA46                 0x1538

#define BRUSH_DATA47                 0x153c

#define BRUSH_DATA48                 0x1540

#define BRUSH_DATA49                 0x1544

#define BRUSH_DATA5                  0x1494

#define BRUSH_DATA50                 0x1548

#define BRUSH_DATA51                 0x154c

#define BRUSH_DATA52                 0x1550

#define BRUSH_DATA53                 0x1554

#define BRUSH_DATA54                 0x1558

#define BRUSH_DATA55                 0x155c

#define BRUSH_DATA56                 0x1560

#define BRUSH_DATA57                 0x1564

#define BRUSH_DATA58                 0x1568

#define BRUSH_DATA59                 0x156c

#define BRUSH_DATA6                  0x1498

#define BRUSH_DATA60                 0x1570

#define BRUSH_DATA61                 0x1574

#define BRUSH_DATA62                 0x1578

#define BRUSH_DATA63                 0x157c

#define BRUSH_DATA7                  0x149c

#define BRUSH_DATA8                  0x14a0

#define BRUSH_DATA9                  0x14a4

#define BRUSH_SCALE                  0x1470

#define BRUSH_Y_X                    0x1474

#define BUS_CNTL                     0x0030

#       define BUS_MASTER_DIS         (1 << 6)

#       define BUS_RD_DISCARD_EN      (1 << 24)

#       define BUS_RD_ABORT_EN        (1 << 25)

#       define BUS_MSTR_DISCONNECT_EN (1 << 28)

#       define BUS_WRT_BURST          (1 << 29)

#       define BUS_READ_BURST         (1 << 30)

#define BUS_CNTL1                    0x0034

#       define BUS_WAIT_ON_LOCK_EN    (1 << 4)

#define CACHE_CNTL                   0x1724

#define CACHE_LINE                   0x0f0c /* PCI */

#define CAP0_TRIG_CNTL               0x0950 /* ? */

#define CAP1_TRIG_CNTL               0x09c0 /* ? */

#define CAPABILITIES_ID              0x0f50 /* PCI */

#define CAPABILITIES_PTR             0x0f34 /* PCI */

#define CLK_PIN_CNTL                 0x0001 /* PLL */

#define CLOCK_CNTL_DATA              0x000c

#define CLOCK_CNTL_INDEX             0x0008

#       define PLL_WR_EN             (1 << 7)

#       define PLL_DIV_SEL           (3 << 8)

#       define PLL2_DIV_SEL_MASK     ~(3 << 8)

#define CLR_CMP_CLR_3D               0x1a24

#define CLR_CMP_CLR_DST              0x15c8

#define CLR_CMP_CLR_SRC              0x15c4

#define CLR_CMP_CNTL                 0x15c0

#       define SRC_CMP_EQ_COLOR      (4 <<  0)

#       define SRC_CMP_NEQ_COLOR     (5 <<  0)

#       define CLR_CMP_SRC_SOURCE    (1 << 24)

#define CLR_CMP_MASK                 0x15cc

#       define CLR_CMP_MSK           0xffffffff

#define CLR_CMP_MASK_3D              0x1A28

#define COMMAND                      0x0f04 /* PCI */

#define COMPOSITE_SHADOW_ID          0x1a0c

#define CONFIG_APER_0_BASE           0x0100

#define CONFIG_APER_1_BASE           0x0104

#define CONFIG_APER_SIZE             0x0108

#define CONFIG_BONDS                 0x00e8

#define CONFIG_CNTL                  0x00e0

#       define CFG_ATI_REV_A11       (0   << 16)

#       define CFG_ATI_REV_A12       (1   << 16)

#       define CFG_ATI_REV_A13       (2   << 16)

#       define CFG_ATI_REV_ID_MASK   (0xf << 16)

#define CONFIG_MEMSIZE               0x00f8

#define CONFIG_MEMSIZE_EMBEDDED      0x0114

#define CONFIG_REG_1_BASE            0x010c

#define CONFIG_REG_APER_SIZE         0x0110

#define CONFIG_XSTRAP                0x00e4

#define CONSTANT_COLOR_C             0x1d34

#       define CONSTANT_COLOR_MASK   0x00ffffff

#       define CONSTANT_COLOR_ONE    0x00ffffff

#       define CONSTANT_COLOR_ZERO   0x00000000

#define CRC_CMDFIFO_ADDR             0x0740

#define CRC_CMDFIFO_DOUT             0x0744

#define CRTC_CRNT_FRAME              0x0214

#define CRTC_EXT_CNTL                0x0054

#       define CRTC_VGA_XOVERSCAN    (1 <<  0)

#       define VGA_ATI_LINEAR        (1 <<  3)

#       define XCRT_CNT_EN           (1 <<  6)

#       define CRTC_HSYNC_DIS        (1 <<  8)

#       define CRTC_VSYNC_DIS        (1 <<  9)

#       define CRTC_DISPLAY_DIS      (1 << 10)

#       define CRTC_SYNC_TRISTAT     (1 << 11)

#       define CRTC_CRT_ON           (1 << 15)

#define CRTC_EXT_CNTL_DPMS_BYTE      0x0055

#       define CRTC_HSYNC_DIS_BYTE   (1 <<  0)

#       define CRTC_VSYNC_DIS_BYTE   (1 <<  1)

#       define CRTC_DISPLAY_DIS_BYTE (1 <<  2)

#define CRTC_GEN_CNTL                0x0050

#       define CRTC_DBL_SCAN_EN      (1 <<  0)

#       define CRTC_INTERLACE_EN     (1 <<  1)

#       define CRTC_CSYNC_EN         (1 <<  4)

#       define CRTC_CUR_EN           (1 << 16)

#       define CRTC_CUR_MODE_MASK    (7 << 17)

#       define CRTC_ICON_EN          (1 << 20)

#       define CRTC_EXT_DISP_EN      (1 << 24)

#       define CRTC_EN               (1 << 25)

#       define CRTC_DISP_REQ_EN_B    (1 << 26)

#define CRTC2_GEN_CNTL               0x03f8

#       define CRTC2_DBL_SCAN_EN     (1 <<  0)

#       define CRTC2_INTERLACE_EN    (1 <<  1)

#       define CRTC2_SYNC_TRISTAT    (1 <<  4)

#       define CRTC2_HSYNC_TRISTAT   (1 <<  5)

#       define CRTC2_VSYNC_TRISTAT   (1 <<  6)

#       define CRTC2_CRT2_ON         (1 <<  7)

#       define CRTC2_ICON_EN         (1 << 15)

#       define CRTC2_CUR_EN          (1 << 16)

#       define CRTC2_CUR_MODE_MASK   (7 << 20)

#       define CRTC2_DISP_DIS        (1 << 23)

#       define CRTC2_EN              (1 << 25)

#       define CRTC2_DISP_REQ_EN_B   (1 << 26)

#       define CRTC2_CSYNC_EN        (1 << 27)

#       define CRTC2_HSYNC_DIS       (1 << 28)

#       define CRTC2_VSYNC_DIS       (1 << 29)

#define CRTC_GUI_TRIG_VLINE          0x0218

#define CRTC_H_SYNC_STRT_WID         0x0204

#       define CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)

#       define CRTC_H_SYNC_STRT_CHAR       (0x3ff <<  3)

#       define CRTC_H_SYNC_STRT_CHAR_SHIFT 3

#       define CRTC_H_SYNC_WID             (0x3f  << 16)

#       define CRTC_H_SYNC_WID_SHIFT       16

#       define CRTC_H_SYNC_POL             (1     << 23)

#define CRTC2_H_SYNC_STRT_WID        0x0304

#       define CRTC2_H_SYNC_STRT_PIX        (0x07  <<  0)

#       define CRTC2_H_SYNC_STRT_CHAR       (0x3ff <<  3)

#       define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3

#       define CRTC2_H_SYNC_WID             (0x3f  << 16)

#       define CRTC2_H_SYNC_WID_SHIFT       16

#       define CRTC2_H_SYNC_POL             (1     << 23)

#define CRTC_H_TOTAL_DISP            0x0200

#       define CRTC_H_TOTAL          (0x03ff << 0)

#       define CRTC_H_TOTAL_SHIFT    0

#       define CRTC_H_DISP           (0x01ff << 16)

#       define CRTC_H_DISP_SHIFT     16

#define CRTC2_H_TOTAL_DISP           0x0300

#       define CRTC2_H_TOTAL         (0x03ff << 0)

#       define CRTC2_H_TOTAL_SHIFT   0

#       define CRTC2_H_DISP          (0x01ff << 16)

#       define CRTC2_H_DISP_SHIFT    16

#define CRTC_OFFSET                  0x0224

#define CRTC2_OFFSET                 0x0324

#define CRTC_OFFSET_CNTL             0x0228

#       define CRTC_TILE_EN          (1 << 15)

#define CRTC2_OFFSET_CNTL            0x0328

#       define CRTC2_TILE_EN         (1 << 15)

#define CRTC_PITCH                   0x022c

#define CRTC2_PITCH                  0x032c

#define CRTC_STATUS                  0x005c

#       define CRTC_VBLANK_SAVE      (1 <<  1)

#       define CRTC_VBLANK_SAVE_CLEAR  (1 <<  1)

#define CRTC2_STATUS                  0x03fc

#       define CRTC2_VBLANK_SAVE      (1 <<  1)

#       define CRTC2_VBLANK_SAVE_CLEAR  (1 <<  1)

#define CRTC_V_SYNC_STRT_WID         0x020c

#       define CRTC_V_SYNC_STRT        (0x7ff <<  0)

#       define CRTC_V_SYNC_STRT_SHIFT  0

#       define CRTC_V_SYNC_WID         (0x1f  << 16)

#       define CRTC_V_SYNC_WID_SHIFT   16

#       define CRTC_V_SYNC_POL         (1     << 23)

#define CRTC2_V_SYNC_STRT_WID        0x030c

#       define CRTC2_V_SYNC_STRT       (0x7ff <<  0)

#       define CRTC2_V_SYNC_STRT_SHIFT 0

#       define CRTC2_V_SYNC_WID        (0x1f  << 16)

#       define CRTC2_V_SYNC_WID_SHIFT  16

#       define CRTC2_V_SYNC_POL        (1     << 23)

#define CRTC_V_TOTAL_DISP            0x0208

#       define CRTC_V_TOTAL          (0x07ff << 0)

#       define CRTC_V_TOTAL_SHIFT    0

#       define CRTC_V_DISP           (0x07ff << 16)

#       define CRTC_V_DISP_SHIFT     16

#define CRTC2_V_TOTAL_DISP           0x0308

#       define CRTC2_V_TOTAL         (0x07ff << 0)

#       define CRTC2_V_TOTAL_SHIFT   0

#       define CRTC2_V_DISP          (0x07ff << 16)

#       define CRTC2_V_DISP_SHIFT    16

#define CRTC_VLINE_CRNT_VLINE        0x0210

#       define CRTC_CRNT_VLINE_MASK  (0x7ff << 16)

#define CRTC2_CRNT_FRAME             0x0314

#define CRTC2_GUI_TRIG_VLINE         0x0318

#define CRTC2_VLINE_CRNT_VLINE       0x0310

#define CRTC8_DATA                   0x03d5 /* VGA, 0x3b5 */

#define CRTC8_IDX                    0x03d4 /* VGA, 0x3b4 */

#define CUR_CLR0                     0x026c

#define CUR_CLR1                     0x0270

#define CUR_HORZ_VERT_OFF            0x0268

#define CUR_HORZ_VERT_POSN           0x0264

#define CUR_OFFSET                   0x0260

#       define CUR_LOCK              (1 << 31)

#define CUR2_CLR0                    0x036c

#define CUR2_CLR1                    0x0370

#define CUR2_HORZ_VERT_OFF           0x0368

#define CUR2_HORZ_VERT_POSN          0x0364

#define CUR2_OFFSET                  0x0360

#       define CUR2_LOCK             (1 << 31)

#define DAC_CNTL                     0x0058

#       define DAC_RANGE_CNTL        (3 <<  0)

#       define DAC_BLANKING          (1 <<  2)

#       define DAC_8BIT_EN           (1 <<  8)

#       define DAC_VGA_ADR_EN        (1 << 13)

#       define DAC_PDWN              (1 << 15)

#       define DAC_MASK_ALL          (0xff << 24)

#define DAC_CNTL2                    0x007c

#       define DAC2_DAC_CLK_SEL      (1 <<  0)

#       define DAC2_DAC2_CLK_SEL     (1 <<  1)

#       define DAC2_PALETTE_ACC_CTL  (1 <<  5)

#define TV_DAC_CNTL                  0x088c

#       define TV_DAC_STD_MASK       0x0300

#       define TV_DAC_RDACPD         (1 <<  24)

#       define TV_DAC_GDACPD         (1 <<  25)

#       define TV_DAC_BDACPD         (1 <<  26)

#define DISP_HW_DEBUG                0x0d14

#       define CRT2_DISP1_SEL        (1 <<  5)

#define DISP_OUTPUT_CNTL             0x0d64

#       define DISP_DAC_SOURCE_MASK  0x03

#       define DISP_DAC_SOURCE_CRTC2 0x01

#define DAC_CRC_SIG                  0x02cc

#define DAC_DATA                     0x03c9 /* VGA */

#define DAC_MASK                     0x03c6 /* VGA */

#define DAC_R_INDEX                  0x03c7 /* VGA */

#define DAC_W_INDEX                  0x03c8 /* VGA */

#define DDA_CONFIG                   0x02e0

#define DDA_ON_OFF                   0x02e4

#define DEFAULT_OFFSET               0x16e0

#define DEFAULT_PITCH                0x16e4

#define DEFAULT_SC_BOTTOM_RIGHT      0x16e8

#       define DEFAULT_SC_RIGHT_MAX  (0x1fff <<  0)

#       define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)

#define DESTINATION_3D_CLR_CMP_VAL   0x1820

#define DESTINATION_3D_CLR_CMP_MSK   0x1824

#define DEVICE_ID                    0x0f02 /* PCI */

#define DISP_MISC_CNTL               0x0d00

#       define SOFT_RESET_GRPH_PP    (1 << 0)

#define DP_BRUSH_BKGD_CLR            0x1478

#define DP_BRUSH_FRGD_CLR            0x147c

#define DP_CNTL                      0x16c0

#       define DST_X_LEFT_TO_RIGHT   (1 <<  0)

#       define DST_Y_TOP_TO_BOTTOM   (1 <<  1)

#define DP_CNTL_XDIR_YDIR_YMAJOR     0x16d0

#       define DST_Y_MAJOR             (1 <<  2)

#       define DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)

#       define DST_X_DIR_LEFT_TO_RIGHT (1 << 31)

#define DP_DATATYPE                  0x16c4

#       define HOST_BIG_ENDIAN_EN    (1 << 29)

#define DP_GUI_MASTER_CNTL           0x146c

#       define GMC_SRC_PITCH_OFFSET_CNTL   (1    <<  0)

#       define GMC_DST_PITCH_OFFSET_CNTL   (1    <<  1)

#       define GMC_SRC_CLIPPING            (1    <<  2)

#       define GMC_DST_CLIPPING            (1    <<  3)

#       define GMC_BRUSH_DATATYPE_MASK     (0x0f <<  4)

#       define GMC_BRUSH_8X8_MONO_FG_BG    (0    <<  4)

#       define GMC_BRUSH_8X8_MONO_FG_LA    (1    <<  4)

#       define GMC_BRUSH_1X8_MONO_FG_BG    (4    <<  4)

#       define GMC_BRUSH_1X8_MONO_FG_LA    (5    <<  4)

#       define GMC_BRUSH_32x1_MONO_FG_BG   (6    <<  4)

#       define GMC_BRUSH_32x1_MONO_FG_LA   (7    <<  4)

#       define GMC_BRUSH_32x32_MONO_FG_BG  (8    <<  4)

#       define GMC_BRUSH_32x32_MONO_FG_LA  (9    <<  4)

#       define GMC_BRUSH_8x8_COLOR         (10   <<  4)

#       define GMC_BRUSH_1X8_COLOR         (12   <<  4)

#       define GMC_BRUSH_SOLID_COLOR       (13   <<  4)

#       define GMC_BRUSH_NONE              (15   <<  4)

#       define GMC_DST_8BPP_CI             (2    <<  8)

#       define GMC_DST_15BPP               (3    <<  8)

#       define GMC_DST_16BPP               (4    <<  8)

#       define GMC_DST_24BPP               (5    <<  8)

#       define GMC_DST_32BPP               (6    <<  8)

#       define GMC_DST_8BPP_RGB            (7    <<  8)

#       define GMC_DST_Y8                  (8    <<  8)

#       define GMC_DST_RGB8                (9    <<  8)

#       define GMC_DST_VYUY                (11   <<  8)

#       define GMC_DST_YVYU                (12   <<  8)

#       define GMC_DST_AYUV444             (14   <<  8)

#       define GMC_DST_ARGB4444            (15   <<  8)

#       define GMC_DST_DATATYPE_MASK       (0x0f <<  8)

#       define GMC_DST_DATATYPE_SHIFT      8

#       define GMC_SRC_DATATYPE_MASK       (3    << 12)

#       define GMC_SRC_DATATYPE_MONO_FG_BG (0    << 12)

#       define GMC_SRC_DATATYPE_MONO_FG_LA (1    << 12)

#       define GMC_SRC_DATATYPE_COLOR      (3    << 12)

#       define GMC_BYTE_PIX_ORDER          (1    << 14)

#       define GMC_BYTE_MSB_TO_LSB         (0    << 14)

#       define GMC_BYTE_LSB_TO_MSB         (1    << 14)

#       define GMC_CONVERSION_TEMP         (1    << 15)

#       define GMC_CONVERSION_TEMP_6500    (0    << 15)

#       define GMC_CONVERSION_TEMP_9300    (1    << 15)

#       define GMC_ROP3_MASK               (0xff << 16)

#       define DP_SRC_SOURCE_MASK          (7    << 24)

#       define DP_SRC_SOURCE_MEMORY        (2    << 24)

#       define DP_SRC_SOURCE_HOST_DATA     (3    << 24)

#       define GMC_3D_FCN_EN               (1    << 27)

#       define GMC_CLR_CMP_CNTL_DIS        (1    << 28)

#       define GMC_AUX_CLIP_DIS            (1    << 29)

#       define GMC_WR_MSK_DIS              (1    << 30)

#       define GMC_LD_BRUSH_Y_X            (1    << 31)

#       define ROP3_ZERO             0x00000000

#       define ROP3_DSa              0x00880000

#       define ROP3_SDna             0x00440000

#       define ROP3_S                0x00cc0000

#       define ROP3_DSna             0x00220000

#       define ROP3_D                0x00aa0000

#       define ROP3_DSx              0x00660000

#       define ROP3_DSo              0x00ee0000

#       define ROP3_DSon             0x00110000

#       define ROP3_DSxn             0x00990000

#       define ROP3_Dn               0x00550000

#       define ROP3_SDno             0x00dd0000

#       define ROP3_Sn               0x00330000

#       define ROP3_DSno             0x00bb0000

#       define ROP3_DSan             0x00770000

#       define ROP3_ONE              0x00ff0000

#       define ROP3_DPa              0x00a00000

#       define ROP3_PDna             0x00500000

#       define ROP3_P                0x00f00000

#       define ROP3_DPna             0x000a0000

#       define ROP3_DPo              0x00fa0000

#       define ROP3_DPon             0x00050000

#       define ROP3_PDxn             0x00a50000

#       define ROP3_DPx              0x005a0000

#       define ROP3_PDno             0x00f50000

#       define ROP3_Pn               0x000f0000

#       define ROP3_DPno             0x00af0000

#       define ROP3_DPan             0x005f0000

#define DP_GUI_MASTER_CNTL_C         0x1c84

#define DP_MIX                       0x16c8

#define DP_SRC_BKGD_CLR              0x15dc

#define DP_SRC_FRGD_CLR              0x15d8

#define DP_WRITE_MASK                0x16cc

#define DST_BRES_DEC                 0x1630

#define DST_BRES_ERR                 0x1628

#define DST_BRES_INC                 0x162c

#define DST_BRES_LNTH                0x1634

#define DST_BRES_LNTH_SUB            0x1638

#define DST_HEIGHT                   0x1410

#define DST_HEIGHT_WIDTH             0x143c

#define DST_HEIGHT_WIDTH_8           0x158c

#define DST_HEIGHT_WIDTH_BW          0x15b4

#define DST_HEIGHT_Y                 0x15a0

#define DST_LINE_START               0x1600

#define DST_LINE_END                 0x1604

#define DST_LINE_PATCOUNT            0x1608

#       define BRES_CNTL_SHIFT       8

#define DST_OFFSET                   0x1404

#define DST_PITCH                    0x1408

#define DST_PITCH_OFFSET             0x142c

#define DST_PITCH_OFFSET_C           0x1c80

#       define PITCH_SHIFT           21

#       define DST_TILE_LINEAR       (0 << 30)

#       define DST_TILE_MACRO        (1 << 30)

#       define DST_TILE_MICRO        (2 << 30)

#       define DST_TILE_BOTH         (3 << 30)

#define DST_WIDTH                    0x140c

#define DST_WIDTH_HEIGHT             0x1598

#define DST_WIDTH_X                  0x1588

#define DST_WIDTH_X_INCY             0x159c

#define DST_X                        0x141c

#define DST_X_SUB                    0x15a4

#define DST_X_Y                      0x1594

#define DST_Y                        0x1420

#define DST_Y_SUB                    0x15a8

#define DST_Y_X                      0x1438

#define FCP_CNTL                     0x0910

#      define FCP0_SRC_PCICLK             0

#      define FCP0_SRC_PCLK               1

#      define FCP0_SRC_PCLKb              2

#      define FCP0_SRC_HREF               3

#      define FCP0_SRC_GND                4

#      define FCP0_SRC_HREFb              5

#define FLUSH_1                      0x1704

#define FLUSH_2                      0x1708

#define FLUSH_3                      0x170c

#define FLUSH_4                      0x1710

#define FLUSH_5                      0x1714

#define FLUSH_6                      0x1718

#define FLUSH_7                      0x171c

#define FOG_3D_TABLE_START           0x1810

#define FOG_3D_TABLE_END             0x1814

#define FOG_3D_TABLE_DENSITY         0x181c

#define FOG_TABLE_INDEX              0x1a14

#define FOG_TABLE_DATA               0x1a18

#define FP_CRTC_H_TOTAL_DISP         0x0250

#define FP_CRTC_V_TOTAL_DISP         0x0254

#define FP_CRTC2_H_TOTAL_DISP        0x0350

#define FP_CRTC2_V_TOTAL_DISP        0x0354

#       define FP_CRTC_H_TOTAL_MASK      0x000003ff

#       define FP_CRTC_H_DISP_MASK       0x01ff0000

#       define FP_CRTC_V_TOTAL_MASK      0x00000fff

#       define FP_CRTC_V_DISP_MASK       0x0fff0000

#       define FP_H_SYNC_STRT_CHAR_MASK  0x00001ff8

#       define FP_H_SYNC_WID_MASK        0x003f0000

#       define FP_V_SYNC_STRT_MASK       0x00000fff

#       define FP_V_SYNC_WID_MASK        0x001f0000

#       define FP_CRTC_H_TOTAL_SHIFT     0x00000000

#       define FP_CRTC_H_DISP_SHIFT      0x00000010

#       define FP_CRTC_V_TOTAL_SHIFT     0x00000000

#       define FP_CRTC_V_DISP_SHIFT      0x00000010

#       define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003

#       define FP_H_SYNC_WID_SHIFT       0x00000010

#       define FP_V_SYNC_STRT_SHIFT      0x00000000

#       define FP_V_SYNC_WID_SHIFT       0x00000010

#define FP_GEN_CNTL                  0x0284

#       define FP_FPON                  (1 <<  0)

#       define FP_TMDS_EN               (1 <<  2)

#       define FP_PANEL_FORMAT          (1 <<  3)

#       define FP_EN_TMDS               (1 <<  7)

#       define FP_DETECT_SENSE          (1 <<  8)

#       define FP_SEL_CRTC2             (1 << 13)

#       define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)

#       define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)

#       define FP_CRTC_DONT_SHADOW_HEND (1 << 17)

#       define FP_CRTC_USE_SHADOW_VEND  (1 << 18)

#       define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)

#       define FP_DFP_SYNC_SEL          (1 << 21)

#       define FP_CRTC_LOCK_8DOT        (1 << 22)

#       define FP_CRT_SYNC_SEL          (1 << 23)

#       define FP_USE_SHADOW_EN         (1 << 24)

#       define FP_CRT_SYNC_ALT          (1 << 26)

#define FP2_GEN_CNTL                 0x0288

#       define FP2_BLANK_EN             (1 <<  1)

#       define FP2_ON                   (1 <<  2)

#       define FP2_PANEL_FORMAT         (1 <<  3)

#       define FP2_SEL_CRTC2            (1 << 13)

#       define FP2_FP_POL               (1 << 16)

#       define FP2_LP_POL               (1 << 17)

#       define FP2_SCK_POL              (1 << 18)

#       define FP2_LCD_CNTL_MASK        (7 << 19)

#       define FP2_PAD_FLOP_EN          (1 << 22)

#       define FP2_CRC_EN               (1 << 23)

#       define FP2_CRC_READ_EN          (1 << 24)

#define FP_H_SYNC_STRT_WID           0x02c4

#define FP_H2_SYNC_STRT_WID          0x03c4

#define FP_HORZ_STRETCH              0x028c

#define FP_HORZ2_STRETCH             0x038c

#       define HORZ_STRETCH_RATIO_MASK 0xffff

#       define HORZ_STRETCH_RATIO_MAX  4096

#       define HORZ_PANEL_SIZE         (0x1ff   << 16)

#       define HORZ_PANEL_SHIFT        16

#       define HORZ_STRETCH_PIXREP     (0      << 25)

#       define HORZ_STRETCH_BLEND      (1      << 26)

#       define HORZ_STRETCH_ENABLE     (1      << 25)

#       define HORZ_AUTO_RATIO         (1      << 27)

#       define HORZ_FP_LOOP_STRETCH    (0x7    << 28)

#       define HORZ_AUTO_RATIO_INC     (1      << 31)

#define FP_V_SYNC_STRT_WID           0x02c8

#define FP_VERT_STRETCH              0x0290

#define FP_V2_SYNC_STRT_WID          0x03c8

#define FP_VERT2_STRETCH             0x0390

#       define VERT_PANEL_SIZE          (0xfff << 12)

#       define VERT_PANEL_SHIFT         12

#       define VERT_STRETCH_RATIO_MASK  0xfff

#       define VERT_STRETCH_RATIO_SHIFT 0

#       define VERT_STRETCH_RATIO_MAX   4096

#       define VERT_STRETCH_ENABLE      (1     << 25)

#       define VERT_STRETCH_LINEREP     (0     << 26)

#       define VERT_STRETCH_BLEND       (1     << 26)

#       define VERT_AUTO_RATIO_EN       (1     << 27)

#       define VERT_STRETCH_RESERVED    0xf1000000

#define GEN_INT_CNTL                 0x0040

#define GEN_INT_STATUS               0x0044

#       define VSYNC_INT_AK          (1 <<  2)

#       define VSYNC_INT             (1 <<  2)

#       define VSYNC2_INT_AK         (1 <<  6)

#       define VSYNC2_INT            (1 <<  6)

#define GENENB                       0x03c3 /* VGA */

#define GENFC_RD                     0x03ca /* VGA */

#define GENFC_WT                     0x03da /* VGA, 0x03ba */

#define GENMO_RD                     0x03cc /* VGA */

#define GENMO_WT                     0x03c2 /* VGA */

#define GENS0                        0x03c2 /* VGA */

#define GENS1                        0x03da /* VGA, 0x03ba */

#define GPIO_MONID                   0x0068 /* DDC interface via I2C */

#define GPIO_MONIDB                  0x006c

#define GPIO_CRT2_DDC                0x006c

#define GPIO_DVI_DDC                 0x0064

#define GPIO_VGA_DDC                 0x0060

#       define GPIO_A_0              (1 <<  0)

#       define GPIO_A_1              (1 <<  1)

#       define GPIO_Y_0              (1 <<  8)

#       define GPIO_Y_1              (1 <<  9)

#       define GPIO_Y_SHIFT_0        8

#       define GPIO_Y_SHIFT_1        9

#       define GPIO_EN_0             (1 << 16)

#       define GPIO_EN_1             (1 << 17)

#       define GPIO_MASK_0           (1 << 24) /*??*/

#       define GPIO_MASK_1           (1 << 25) /*??*/

#define GRPH8_DATA                   0x03cf /* VGA */

#define GRPH8_IDX                    0x03ce /* VGA */

#define GUI_SCRATCH_REG0             0x15e0

#define GUI_SCRATCH_REG1             0x15e4

#define GUI_SCRATCH_REG2             0x15e8

#define GUI_SCRATCH_REG3             0x15ec

#define GUI_SCRATCH_REG4             0x15f0

#define GUI_SCRATCH_REG5             0x15f4

#define HEADER                       0x0f0e /* PCI */

#define HOST_DATA0                   0x17c0

#define HOST_DATA1                   0x17c4

#define HOST_DATA2                   0x17c8

#define HOST_DATA3                   0x17cc

#define HOST_DATA4                   0x17d0

#define HOST_DATA5                   0x17d4

#define HOST_DATA6                   0x17d8

#define HOST_DATA7                   0x17dc

#define HOST_DATA_LAST               0x17e0

#define HOST_PATH_CNTL               0x0130

#       define HDP_SOFT_RESET        (1 << 26)

#define HTOTAL_CNTL                  0x0009 /* PLL */

#define HTOTAL2_CNTL                 0x002e /* PLL */

#define I2C_CNTL_1                   0x0094 /* ? */

#define DVI_I2C_CNTL_1               0x02e4 /* ? */

#define INTERRUPT_LINE               0x0f3c /* PCI */

#define INTERRUPT_PIN                0x0f3d /* PCI */

#define IO_BASE                      0x0f14 /* PCI */

#define LATENCY                      0x0f0d /* PCI */

#define LEAD_BRES_DEC                0x1608

#define LEAD_BRES_LNTH               0x161c

#define LEAD_BRES_LNTH_SUB           0x1624

#define LVDS_GEN_CNTL                0x02d0

#       define LVDS_ON               (1   <<  0)

#       define LVDS_DISPLAY_DIS      (1   <<  1)

#       define LVDS_PANEL_TYPE       (1   <<  2)

#       define LVDS_PANEL_FORMAT     (1   <<  3)

#       define LVDS_EN               (1   <<  7)

#       define LVDS_DIGON            (1   << 18)

#       define LVDS_BLON             (1   << 19)

#       define LVDS_SEL_CRTC2        (1   << 23)

#define LVDS_PLL_CNTL                0x02d4

#       define HSYNC_DELAY_SHIFT     28

#       define HSYNC_DELAY_MASK      (0xf << 28)

#define MAX_LATENCY                  0x0f3f /* PCI */

#define MC_AGP_LOCATION              0x014c

#define MC_FB_LOCATION               0x0148

#define MCLK_CNTL                    0x0012 /* PLL */

#       define FORCEON_MCLKA         (1 << 16)

#       define FORCEON_MCLKB         (1 << 17)

#       define FORCEON_YCLKA         (1 << 18)

#       define FORCEON_YCLKB         (1 << 19)

#       define FORCEON_MC            (1 << 20)

#       define FORCEON_AIC           (1 << 21)

#define MDGPIO_A_REG                 0x01ac

#define MDGPIO_EN_REG                0x01b0

#define MDGPIO_MASK                  0x0198

#define MDGPIO_Y_REG                 0x01b4

#define MEM_ADDR_CONFIG              0x0148

#define MEM_BASE                     0x0f10 /* PCI */

#define MEM_CNTL                     0x0140

#define MEM_INIT_LAT_TIMER           0x0154

#define MEM_INTF_CNTL                0x014c

#define MEM_SDRAM_MODE_REG           0x0158

#define MEM_STR_CNTL                 0x0150

#define MEM_VGA_RP_SEL               0x003c

#define MEM_VGA_WP_SEL               0x0038