| 2 |
- |
1 |
enum {
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2 |
BusCBUS = 0, /* Corollary CBUS */
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3 |
BusCBUSII, /* Corollary CBUS II */
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4 |
BusEISA, /* Extended ISA */
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5 |
BusFUTURE, /* IEEE Futurebus */
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6 |
BusINTERN, /* Internal bus */
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7 |
BusISA, /* Industry Standard Architecture */
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8 |
BusMBI, /* Multibus I */
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9 |
BusMBII, /* Multibus II */
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10 |
BusMCA, /* Micro Channel Architecture */
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11 |
BusMPI, /* MPI */
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12 |
BusMPSA, /* MPSA */
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13 |
BusNUBUS, /* Apple Macintosh NuBus */
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14 |
BusPCI, /* Peripheral Component Interconnect */
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15 |
BusPCMCIA, /* PC Memory Card International Association */
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16 |
BusTC, /* DEC TurboChannel */
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17 |
BusVL, /* VESA Local bus */
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18 |
BusVME, /* VMEbus */
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19 |
BusXPRESS, /* Express System Bus */
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20 |
BUSUNKNOWN = -1
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21 |
};
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22 |
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23 |
#define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
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24 |
#define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
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25 |
#define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
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26 |
#define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
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27 |
#define BUSTYPE(tbdf) ((tbdf)>>24)
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28 |
#define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
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29 |
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30 |
/*
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31 |
* PCI support code.
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32 |
*/
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33 |
enum { /* type 0 & type 1 pre-defined header */
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34 |
PciVID = 0x00, /* vendor ID */
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35 |
PciDID = 0x02, /* device ID */
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36 |
PciPCR = 0x04, /* command */
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37 |
PciPSR = 0x06, /* status */
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38 |
PciRID = 0x08, /* revision ID */
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39 |
PciCCRp = 0x09, /* programming interface class code */
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40 |
PciCCRu = 0x0A, /* sub-class code */
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41 |
PciCCRb = 0x0B, /* base class code */
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42 |
PciCLS = 0x0C, /* cache line size */
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43 |
PciLTR = 0x0D, /* latency timer */
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44 |
PciHDT = 0x0E, /* header type */
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45 |
PciBST = 0x0F, /* BIST */
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46 |
};
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47 |
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48 |
/* ccrb (base class code) values; controller types */
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49 |
enum {
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50 |
Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
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51 |
Pcibcstore = 1, /* mass storage */
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52 |
Pcibcnet = 2, /* network */
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53 |
Pcibcdisp = 3, /* display */
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54 |
Pcibcmmedia = 4, /* multimedia */
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55 |
Pcibcmem = 5, /* memory */
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56 |
Pcibcbridge = 6, /* bridge */
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57 |
Pcibccomm = 7, /* simple comms (e.g., serial) */
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58 |
Pcibcbasesys = 8, /* base system */
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59 |
Pcibcinput = 9, /* input */
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60 |
Pcibcdock = 0xa, /* docking stations */
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61 |
Pcibcproc = 0xb, /* processors */
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62 |
Pcibcserial = 0xc, /* serial bus (e.g., USB) */
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63 |
Pcibcwireless = 0xd, /* wireless */
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64 |
Pcibcintell = 0xe, /* intelligent i/o */
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65 |
Pcibcsatcom = 0xf, /* satellite comms */
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66 |
Pcibccrypto = 0x10, /* encryption/decryption */
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67 |
Pcibcdacq = 0x11, /* data acquisition & signal proc. */
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68 |
};
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69 |
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70 |
/* ccru (sub-class code) values; common cases only */
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71 |
enum {
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72 |
/* mass storage */
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73 |
Pciscscsi = 0, /* SCSI */
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74 |
Pciscide = 1, /* IDE (ATA) */
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75 |
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76 |
/* network */
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77 |
Pciscether = 0, /* Ethernet */
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78 |
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79 |
/* display */
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80 |
Pciscvga = 0, /* VGA */
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81 |
Pciscxga = 1, /* XGA */
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82 |
Pcisc3d = 2, /* 3D */
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83 |
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84 |
/* bridges */
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85 |
Pcischostpci = 0, /* host/pci */
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86 |
Pciscpcicpci = 1, /* pci/pci */
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87 |
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88 |
/* simple comms */
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89 |
Pciscserial = 0, /* 16450, etc. */
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90 |
Pciscmultiser = 1, /* multiport serial */
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91 |
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92 |
/* serial bus */
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93 |
Pciscusb = 3, /* USB */
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94 |
};
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95 |
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96 |
enum { /* type 0 pre-defined header */
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97 |
PciCIS = 0x28, /* cardbus CIS pointer */
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98 |
PciSVID = 0x2C, /* subsystem vendor ID */
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99 |
PciSID = 0x2E, /* cardbus CIS pointer */
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100 |
PciEBAR0 = 0x30, /* expansion ROM base address */
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101 |
PciMGNT = 0x3E, /* burst period length */
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102 |
PciMLT = 0x3F, /* maximum latency between bursts */
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103 |
};
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104 |
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105 |
enum { /* type 1 pre-defined header */
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106 |
PciPBN = 0x18, /* primary bus number */
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107 |
PciSBN = 0x19, /* secondary bus number */
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108 |
PciUBN = 0x1A, /* subordinate bus number */
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109 |
PciSLTR = 0x1B, /* secondary latency timer */
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110 |
PciIBR = 0x1C, /* I/O base */
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111 |
PciILR = 0x1D, /* I/O limit */
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112 |
PciSPSR = 0x1E, /* secondary status */
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113 |
PciMBR = 0x20, /* memory base */
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114 |
PciMLR = 0x22, /* memory limit */
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115 |
PciPMBR = 0x24, /* prefetchable memory base */
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116 |
PciPMLR = 0x26, /* prefetchable memory limit */
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117 |
PciPUBR = 0x28, /* prefetchable base upper 32 bits */
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118 |
PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
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119 |
PciIUBR = 0x30, /* I/O base upper 16 bits */
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120 |
PciIULR = 0x32, /* I/O limit upper 16 bits */
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121 |
PciEBAR1 = 0x28, /* expansion ROM base address */
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122 |
PciBCR = 0x3E, /* bridge control register */
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123 |
};
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124 |
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125 |
enum { /* type 2 pre-defined header */
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126 |
PciCBExCA = 0x10,
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127 |
PciCBSPSR = 0x16,
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128 |
PciCBPBN = 0x18, /* primary bus number */
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129 |
PciCBSBN = 0x19, /* secondary bus number */
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130 |
PciCBUBN = 0x1A, /* subordinate bus number */
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131 |
PciCBSLTR = 0x1B, /* secondary latency timer */
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132 |
PciCBMBR0 = 0x1C,
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133 |
PciCBMLR0 = 0x20,
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134 |
PciCBMBR1 = 0x24,
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135 |
PciCBMLR1 = 0x28,
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136 |
PciCBIBR0 = 0x2C, /* I/O base */
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137 |
PciCBILR0 = 0x30, /* I/O limit */
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138 |
PciCBIBR1 = 0x34, /* I/O base */
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139 |
PciCBILR1 = 0x38, /* I/O limit */
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140 |
PciCBSVID = 0x40, /* subsystem vendor ID */
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141 |
PciCBSID = 0x42, /* subsystem ID */
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142 |
PciCBLMBAR = 0x44, /* legacy mode base address */
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143 |
};
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144 |
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145 |
typedef struct Pcisiz Pcisiz;
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146 |
struct Pcisiz
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147 |
{
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148 |
Pcidev* dev;
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149 |
int siz;
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150 |
int bar;
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151 |
};
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152 |
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153 |
typedef struct Pcidev Pcidev;
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154 |
struct Pcidev
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155 |
{
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156 |
int tbdf; /* type+bus+device+function */
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157 |
ushort vid; /* vendor ID */
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158 |
ushort did; /* device ID */
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159 |
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160 |
ushort pcr;
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161 |
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162 |
uchar rid;
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163 |
uchar ccrp;
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164 |
uchar ccru;
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165 |
uchar ccrb;
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166 |
uchar cls;
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167 |
uchar ltr;
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168 |
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169 |
struct {
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170 |
ulong bar; /* base address */
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171 |
int size;
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172 |
} mem[6];
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173 |
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174 |
struct {
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175 |
ulong bar;
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176 |
int size;
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177 |
} rom;
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178 |
uchar intl; /* interrupt line */
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179 |
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180 |
Pcidev* list;
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181 |
Pcidev* link; /* next device on this bno */
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182 |
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183 |
Pcidev* bridge; /* down a bus */
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184 |
struct {
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185 |
ulong bar;
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186 |
int size;
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187 |
} ioa, mema;
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188 |
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189 |
int pmrb; /* power management register block */
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190 |
};
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191 |
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192 |
#define PCIWINDOW 0
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193 |
#define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
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194 |
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195 |
/*
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196 |
* Kirkwood stuff
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197 |
*/
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198 |
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199 |
enum {
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200 |
AddrEfuse = PHYSIO+0x1008c,
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201 |
Addrpci = PHYSIO+0x40000, /* for registers below */
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202 |
Addrpcibase = PHYSIO+0x41800, /* for registers below */
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203 |
AddrMpp = PHYSIO+0x10000,
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204 |
AddrSdio = PHYSIO+0x90000,
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205 |
};
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206 |
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207 |
enum {
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208 |
Socrevz0,
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209 |
Socreva0 = 2,
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210 |
Socreva1,
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211 |
};
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212 |
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213 |
enum {
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214 |
/* registers; if we actually use these, change to soc.pci(base)->reg */
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215 |
PciBAR0 = Addrpcibase + 4, /* base address */
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216 |
PciBAR1 = Addrpcibase + 8,
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217 |
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218 |
PciCP = Addrpci + 0x64, /* capabilities pointer */
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219 |
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220 |
PciINTL = Addrpci + 0x3c, /* interrupt line */
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221 |
PciINTP = PciINTL + 1, /* interrupt pin */
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222 |
};
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223 |
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224 |
/*
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225 |
* interrupt stuff
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226 |
*/
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227 |
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228 |
enum {
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229 |
Irqlo, Irqhi, Irqbridge,
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230 |
};
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231 |
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232 |
enum {
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233 |
/* main interrupt cause low register bit #s (LE) */
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234 |
IRQ0hisum, /* summary of main intr high cause reg */
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235 |
IRQ0bridge,
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236 |
IRQ0h2cdoorbell,
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237 |
IRQ0c2hdoorbell,
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238 |
_IRQ0reserved0,
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239 |
IRQ0xor0chan0,
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240 |
IRQ0xor0chan1,
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241 |
IRQ0xor1chan0,
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242 |
IRQ0xor1chan1,
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243 |
IRQ0pex0int, /* pex = pci-express */
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244 |
_IRQ0reserved1,
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245 |
IRQ0gbe0sum,
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246 |
IRQ0gbe0rx,
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247 |
IRQ0gbe0tx,
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248 |
IRQ0gbe0misc,
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249 |
IRQ0gbe1sum,
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250 |
IRQ0gbe1rx,
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251 |
IRQ0gbe1tx,
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252 |
IRQ0gbe1misc,
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253 |
IRQ0usb0,
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254 |
_IRQ0reserved2,
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255 |
IRQ0sata,
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256 |
IRQ0crypto,
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257 |
IRQ0spi,
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258 |
IRQ0audio,
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259 |
_IRQ0reserved3,
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260 |
IRQ0ts0,
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261 |
_IRQ0reserved4,
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262 |
IRQ0sdio,
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263 |
IRQ0twsi,
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264 |
IRQ0avb,
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265 |
IRQ0tdm,
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266 |
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267 |
/* main interrupt cause high register bit #s (LE) */
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268 |
_IRQ1reserved0 = 0,
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269 |
IRQ1uart0,
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270 |
IRQ1uart1,
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271 |
IRQ1gpiolo0,
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272 |
IRQ1gpiolo1,
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273 |
IRQ1gpiolo2,
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274 |
IRQ1gpiolo3,
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275 |
IRQ1gpiohi0,
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276 |
IRQ1gpiohi1,
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277 |
IRQ1gpiohi2,
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278 |
IRQ1gpiohi3,
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279 |
IRQ1xor0err,
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280 |
IRQ1xor1err,
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281 |
IRQ1pex0err,
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282 |
_IRQ1reserved1,
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283 |
IRQ1gbe0err,
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284 |
IRQ1gbe1err,
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285 |
IRQ1usberr,
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286 |
IRQ1cryptoerr,
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287 |
IRQ1audioerr,
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288 |
_IRQ1reserved2,
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289 |
_IRQ1reserved3,
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290 |
IRQ1rtc,
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291 |
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292 |
/* bridged-interrupt causes */
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293 |
IRQcpuself = 0,
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294 |
IRQcputimer0,
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295 |
IRQcputimer1,
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296 |
IRQcputimerwd,
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297 |
IRQaccesserr,
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298 |
};
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299 |
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|
300 |
/*
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|
301 |
* interrupt controller
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302 |
*/
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303 |
typedef struct IntrReg IntrReg;
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304 |
struct IntrReg
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|
305 |
{
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306 |
struct {
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|
307 |
ulong irq; /* main intr cause reg (ro) */
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308 |
ulong irqmask;
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309 |
ulong fiqmask;
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310 |
ulong epmask;
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|
311 |
} lo, hi;
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312 |
};
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313 |
|
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|
314 |
/*
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|
315 |
* CPU control & status (archkw.c and trap.c)
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|
316 |
*/
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|
317 |
typedef struct CpucsReg CpucsReg;
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|
318 |
struct CpucsReg
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|
319 |
{
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|
320 |
ulong cpucfg;
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321 |
ulong cpucsr;
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322 |
ulong rstout;
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323 |
ulong softreset;
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324 |
ulong irq; /* mbus(-l) bridge interrupt cause */
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325 |
ulong irqmask; /* ⋯ mask */
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326 |
ulong mempm; /* memory power mgmt. control */
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|
327 |
ulong clockgate; /* clock enable bits */
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328 |
ulong biu;
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329 |
ulong pad0;
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|
330 |
ulong l2cfg; /* turn l2 cache on or off, set coherency */
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|
331 |
ulong pad1[2];
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|
332 |
ulong l2tm0;
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|
333 |
ulong l2tm1;
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|
334 |
ulong pad2[2];
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335 |
ulong l2pm;
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336 |
ulong ram0;
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337 |
ulong ram1;
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338 |
ulong ram2;
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|
339 |
ulong ram3;
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|
340 |
};
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341 |
|
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|
342 |
enum {
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|
343 |
/* cpucfg bits */
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|
344 |
Cfgvecinithi = 1<<1, /* boot at 0xffff0000, not 0; default 1 */
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|
345 |
Cfgbigendreset = 3<<1, /* init. as big-endian at reset; default 0 */
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|
346 |
Cfgiprefetch = 1<<16, /* instruction prefetch enable */
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|
347 |
Cfgdprefetch = 1<<17, /* data prefetch enable */
|
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|
348 |
|
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|
349 |
/* cpucsr bits */
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|
350 |
Reset = 1<<1, /* reset cpu core */
|
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|
351 |
|
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|
352 |
/* rstout bits */
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|
353 |
RstoutPex = 1<<0, /* assert RSTOUTn at pci-e reset */
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|
354 |
RstoutWatchdog = 1<<1, /* assert RSTOUTn at watchdog timeout */
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|
355 |
RstoutSoft = 1<<2, /* assert RSTOUTn at sw reset */
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|
356 |
|
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|
357 |
/* softreset bits */
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|
358 |
ResetSystem = 1<<0, /* assert RSTOUTn pin on SoftRstOutEn */
|
|
|
359 |
|
|
|
360 |
/* l2cfg bits */
|
|
|
361 |
L2ecc = 1<<2,
|
|
|
362 |
L2exists = 1<<3, /* l2 cache doesn't ignore cpu */
|
|
|
363 |
L2writethru = 1<<4, /* always WT, else see PTE C & B */
|
|
|
364 |
};
|
|
|
365 |
|
|
|
366 |
enum {
|
|
|
367 |
/* from 88f6281 func'l specs (MV-S104860-00), tables 2 & 3, chapter 2 */
|
|
|
368 |
Targdram = 0, /* ddr sdram */
|
|
|
369 |
Targflash = 1,
|
|
|
370 |
Targcesasram = 3, /* security accelerator sram */
|
|
|
371 |
|
|
|
372 |
/* attributes */
|
|
|
373 |
Attrcs0 = 0xe, /* chip select 0 (low dram) */
|
|
|
374 |
Attrcs1 = 0xd, /* chip select 1 (high dram) */
|
|
|
375 |
Attrbootrom = 0x1d,
|
|
|
376 |
Attrspi = 0x1e,
|
|
|
377 |
Attrnand = 0x2f,
|
|
|
378 |
|
|
|
379 |
Winenable = 1<<0,
|
|
|
380 |
};
|
|
|
381 |
|
|
|
382 |
typedef struct Pciex Pciex;
|
|
|
383 |
struct Pciex {
|
|
|
384 |
ushort venid; /* 0x11ab means Marvell */
|
|
|
385 |
ushort devid; /* 0x6281 means 6281 */
|
|
|
386 |
ulong csr;
|
|
|
387 |
ulong revid;
|
|
|
388 |
ulong bistcache; /* bist hdr type & cache-line size */
|
|
|
389 |
ulong bar0;
|
|
|
390 |
ulong bar0hi;
|
|
|
391 |
ulong bar1;
|
|
|
392 |
ulong bar1hi;
|
|
|
393 |
ulong bar2;
|
|
|
394 |
ulong bar2hi;
|
|
|
395 |
ulong _pad0;
|
|
|
396 |
ushort ssvenid; /* 0x11ab means Marvell */
|
|
|
397 |
ushort ssdevid; /* 0x11ab means Marvell */
|
|
|
398 |
ulong rombar;
|
|
|
399 |
ulong caplist;
|
|
|
400 |
ulong _pad1;
|
|
|
401 |
ulong intrpinline; /* interrupt pin & line */
|
|
|
402 |
ulong pmcap; /* power mgmt. capability header */
|
|
|
403 |
ulong pmcsr; /* power mgmt. control & status */
|
|
|
404 |
ulong _pad2[2];
|
|
|
405 |
ulong msictl; /* msi message control */
|
|
|
406 |
ulong msiaddr;
|
|
|
407 |
ulong msiaddrhi;
|
|
|
408 |
ulong msidata;
|
|
|
409 |
ulong cap;
|
|
|
410 |
ulong devcap;
|
|
|
411 |
ulong devcsr;
|
|
|
412 |
ulong linkcap;
|
|
|
413 |
ulong linkcsr;
|
|
|
414 |
|
|
|
415 |
uchar _pad[0x40100-0x40074];
|
|
|
416 |
ulong errrep; /* advanced error report header */
|
|
|
417 |
ulong uncorrerr; /* uncorrectable error status */
|
|
|
418 |
ulong uncorrerrmask; /* uncorrectable error mask */
|
|
|
419 |
ulong uncorrerrsev; /* uncorrectable error severity */
|
|
|
420 |
ulong correrr; /* correctable error status */
|
|
|
421 |
ulong correrrmask; /* correctable error mask */
|
|
|
422 |
ulong errcap; /* advanced error capability & ctl. */
|
|
|
423 |
ulong hdrlog[4]; /* header log */
|
|
|
424 |
/* continues with more rubbish at 0x41a00. some day... */
|
|
|
425 |
};
|