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/*
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* sheevaplug machine assist
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* arm926ej-s processor at 1.2GHz
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*
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* loader uses R11 as scratch.
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* R9 and R10 are used for `extern register' variables.
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*
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* ARM v7 arch. ref. man. (I know, this is v5) §B1.3.3 that
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* we don't need barriers around moves to CPSR. The ARM v6 manual
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* seems to be silent on the subject.
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*/
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#include "arm.s"
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/*
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* MCR and MRC are counter-intuitively named.
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* MCR coproc, opcode1, Rd, CRn, CRm[, opcode2] # arm -> coproc
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* MRC coproc, opcode1, Rd, CRn, CRm[, opcode2] # coproc -> arm
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*/
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/*
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* Entered here from Das U-Boot with MMU disabled.
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* Until the MMU is enabled it is OK to call functions provided
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* they are within ±32MiB relative and do not require any
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* local variables or more than one argument (i.e. there is
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* no stack).
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*/
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TEXT _start(SB), 1, $-4
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MOVW $setR12(SB), R12 /* load the SB */
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_main:
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/* SVC mode, interrupts disabled */
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
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MOVW R1, CPSR
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BARRIERS
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/*
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* disable the MMU & caches,
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* switch to system permission & 32-bit addresses.
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*/
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MOVW $(CpCsystem|CpCd32|CpCi32), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0)
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ISB
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/*
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* disable the Sheevaplug's L2 cache, invalidate all caches
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*/
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/* flush caches. 926ejs manual says we have to do it iteratively. */
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_dwbinv0:
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MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
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BNE _dwbinv0
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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/* make the l2 cache pay attention and disable resets */
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MOVW $(PHYSIO+0x20100), R1 /* CPUCSREG */
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MOVW $0, R0
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MOVW R0, 8(R1) /* cpu->rstout = 0; */
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MOVW (4*10)(R1), R2
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ORR $(1<<3), R2 /* cpu->l2cfg |= L2exists */
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MOVW R2, (4*10)(R1)
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ISB
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/* invalidate l2 cache */
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
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ISB
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/* disable l2 cache. do this while l1 caches are off */
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MRC CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
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/* disabling write allocation is probably for cortex-a8 errata 460075 */
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/* l2 off, no wr alloc, no streaming */
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BIC $(CpTCl2ena | CpTCl2wralloc | CpTCldcstream), R1
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MCR CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
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BARRIERS
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/* flush caches. 926ejs manual says we have to do it iteratively. */
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_dwbinv1:
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MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
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BNE _dwbinv1
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BARRIERS
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PUTC('\r')
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/* turn off watchdog; see clock.c */
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MOVW $(PHYSIO+0x20300), R1 /* tmr = (TimerReg *)soc.clock; */
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MOVW $0, R0
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MOVW R0, 0(R1) /* tmr->ctl = 0; */
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BARRIERS
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/* clear Mach */
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MOVW $0, R0
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MOVW $PADDR(MACHADDR), R4 /* address of Mach */
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_machZ:
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MOVW R0, (R4)
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ADD $4, R4 /* bump PTE address */
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CMP.S $PADDR(L1+L1X(0)), R4
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BNE _machZ
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/*
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* set up the MMU page table
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*/
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/* clear all PTEs first, to provide a default */
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PUTC('\n')
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MOVW $PADDR(L1+L1X(0)), R4 /* address of PTE for 0 */
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_ptenv0:
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ZEROPTE()
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CMP.S $PADDR(L1+16*KiB), R4
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BNE _ptenv0
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/* double map of PHYSDRAM, KZERO to PHYSDRAM for first few MBs */
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $PHYSDRAM, R3 /* pa */
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MOVW $PADDR(L1+L1X(PHYSDRAM)), R4 /* address of PTE for PHYSDRAM */
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MOVW $16, R5
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_ptdbl:
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FILLPTE()
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SUB.S $1, R5
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BNE _ptdbl
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/*
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* back up and fill in PTEs for memory at KZERO
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* there is 1 bank of 512MB of SDRAM at PHYSDRAM
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*/
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $PHYSDRAM, R3
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MOVW $PADDR(L1+L1X(KZERO)), R4 /* start with PTE for KZERO */
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MOVW $512, R5 /* inner loop count */
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_ptekrw: /* set PTEs for 512MiB */
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FILLPTE()
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SUB.S $1, R5
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BNE _ptekrw
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/*
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* back up and fill in PTE for MMIO
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*/
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MOVW $PTEIO, R2 /* PTE bits */
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MOVW $PHYSIO, R3
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MOVW $PADDR(L1+L1X(VIRTIO)), R4 /* start with PTE for VIRTIO */
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FILLPTE()
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/* mmu.c sets up the vectors later */
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/*
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* set up a temporary stack; avoid data & bss segments
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*/
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MOVW $(PHYSDRAM | (400*1024*1024)), R13
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PUTC('P')
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/* set the domain access control */
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MOVW $Client, R0
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BL dacput(SB)
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/* set the translation table base */
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MOVW $PADDR(L1), R0
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BL ttbput(SB)
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MOVW $0, R0
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BL pidput(SB) /* paranoia */
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/* the little dance to turn the MMU & caches on */
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PUTC('l')
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BL cacheuwbinv(SB)
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BL mmuinvalidate(SB)
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BL mmuenable(SB)
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PUTC('a')
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/* warp the PC into the virtual map */
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MOVW $KZERO, R0
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BL _r15warp(SB)
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/*
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* now running at KZERO+something!
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*/
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MOVW $setR12(SB), R12 /* reload the SB */
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/*
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* set up temporary stack again, in case we've just switched
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* to a new register set.
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*/
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MOVW $(KZERO|(400*1024*1024)), R13
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/* can now execute arbitrary C code */
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BL cacheuwbinv(SB)
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PUTC('n')
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/* undo double map of 0, KZERO */
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MOVW $PADDR(L1+L1X(0)), R4 /* address of PTE for 0 */
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MOVW $0, R0
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MOVW $16, R5
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_ptudbl:
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MOVW R0, (R4)
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ADD $4, R4 /* bump PTE address */
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ADD $MiB, R0 /* bump pa */
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SUB.S $1, R5
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BNE _ptudbl
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BARRIERS
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvd), CpTLBinvse
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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PUTC(' ')
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/* pass Mach to main and set up the stack */
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MOVW $(MACHADDR), R0 /* Mach */
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MOVW R0, R13
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ADD $(MACHSIZE), R13 /* stack pointer */
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SUB $4, R13 /* space for link register */
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BL main(SB) /* void main(Mach*) */
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/* fall through */
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211 |
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/* not used */
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TEXT _reset(SB), 1, $-4
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/* turn the caches off */
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R0
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MOVW R0, CPSR
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BARRIERS
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BL cacheuwbinv(SB)
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCwb|CpCicache|CpCdcache|CpCalign), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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PUTC('R')
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/* redo double map of 0, KZERO */
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MOVW $(L1+L1X(0)), R4 /* address of PTE for 0 */
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $0, R3
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MOVW $16, R5
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_ptrdbl:
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ORR R3, R2, R1 /* first identity-map 0 to 0, etc. */
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MOVW R1, (R4)
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ADD $4, R4 /* bump PTE address */
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ADD $MiB, R3 /* bump pa */
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SUB.S $1, R5
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BNE _ptrdbl
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237 |
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238 |
BARRIERS
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PUTC('e')
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvd), CpTLBinv
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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244 |
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/* back to 29- or 26-bit addressing, mainly for SB */
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCd32|CpCi32), R0
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248 |
MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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/* turn the MMU off */
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MOVW $PHYSDRAM, R0
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BL _r15warp(SB)
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BL mmuinvalidate(SB)
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BL mmudisable(SB)
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256 |
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257 |
PUTC('s')
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/* set new reset vector */
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259 |
MOVW $0, R2
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260 |
MOVW $0xe59ff018, R3 /* MOVW 0x18(R15), R15 */
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MOVW R3, (R2)
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PUTC('e')
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263 |
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MOVW $PHYSBOOTROM, R3
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MOVW R3, 0x20(R2) /* where $0xe59ff018 jumps to */
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BARRIERS
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PUTC('t')
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PUTC('\r')
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PUTC('\n')
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270 |
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271 |
/* ...and jump to it */
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MOVW R2, R15 /* software reboot */
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_limbo: /* should not get here... */
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274 |
B _limbo /* ... and can't get out */
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275 |
BL _div(SB) /* hack to load _div, etc. */
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276 |
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277 |
TEXT _r15warp(SB), 1, $-4
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278 |
BIC $KSEGM, R14
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279 |
ORR R0, R14
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280 |
BIC $KSEGM, R13
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281 |
ORR R0, R13
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282 |
RET
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283 |
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284 |
/* clobbers R1, R6 */
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285 |
TEXT myputc(SB), 1, $-4
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286 |
MOVW $PHYSCONS, R6
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287 |
_busy:
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288 |
MOVW 20(R6), R1
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289 |
BIC.S $~(1<<5), R1 /* (x->lsr & LSRthre) == 0? */
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290 |
BEQ _busy
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291 |
MOVW R3, (R6) /* print */
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292 |
ISB
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293 |
RET
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294 |
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295 |
/*
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296 |
* l1 caches
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297 |
*/
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298 |
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299 |
TEXT l1cacheson(SB), 1, $-4
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300 |
MOVW CPSR, R5
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301 |
ORR $(PsrDirq|PsrDfiq), R5, R4
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302 |
MOVW R4, CPSR /* splhi */
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303 |
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304 |
MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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305 |
ORR $(CpCdcache|CpCicache|CpCwb), R0
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306 |
MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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307 |
BARRIERS
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308 |
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309 |
MOVW R5, CPSR /* splx */
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310 |
RET
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311 |
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312 |
TEXT l1cachesoff(SB), 1, $-4
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313 |
MOVM.DB.W [R14], (SP) /* save lr on stack */
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314 |
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315 |
MOVW CPSR, R5
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316 |
ORR $(PsrDirq|PsrDfiq), R5, R4
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317 |
MOVW R4, CPSR /* splhi */
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318 |
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319 |
BL cacheuwbinv(SB)
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320 |
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321 |
MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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322 |
BIC $(CpCdcache|CpCicache|CpCwb), R0
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323 |
MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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324 |
BARRIERS
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325 |
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326 |
MOVW R5, CPSR /* splx */
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327 |
MOVM.IA.W (SP), [R14] /* restore lr */
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328 |
RET
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329 |
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330 |
/*
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331 |
* cache* functions affect only the L1 caches, which are VIVT.
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332 |
*/
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333 |
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334 |
TEXT cachedwb(SB), 1, $-4 /* D writeback */
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335 |
MOVW CPSR, R3 /* splhi */
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336 |
ORR $(PsrDirq), R3, R1
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337 |
MOVW R1, CPSR
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338 |
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339 |
BARRIERS /* force outstanding stores to cache */
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340 |
/* keep writing back dirty cache lines until no more exist */
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341 |
_dwb:
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342 |
MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwb), CpCACHEtest
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343 |
BNE _dwb
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344 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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345 |
BARRIERS
|
|
|
346 |
|
|
|
347 |
MOVW R3, CPSR /* splx */
|
|
|
348 |
RET
|
|
|
349 |
|
|
|
350 |
TEXT cachedwbse(SB), 1, $-4 /* D writeback SE */
|
|
|
351 |
MOVW R0, R2 /* first arg: address */
|
|
|
352 |
|
|
|
353 |
MOVW CPSR, R3 /* splhi */
|
|
|
354 |
ORR $(PsrDirq), R3, R1
|
|
|
355 |
MOVW R1, CPSR
|
|
|
356 |
|
|
|
357 |
BARRIERS /* force outstanding stores to cache */
|
|
|
358 |
MOVW 4(FP), R1 /* second arg: size */
|
|
|
359 |
|
|
|
360 |
// CMP.S $(4*1024), R1
|
|
|
361 |
// BGT _dwb
|
|
|
362 |
ADD R2, R1
|
|
|
363 |
BIC $(CACHELINESZ-1), R2
|
|
|
364 |
_dwbse:
|
|
|
365 |
MCR CpSC, 0, R2, C(CpCACHE), C(CpCACHEwb), CpCACHEse
|
|
|
366 |
ADD $CACHELINESZ, R2
|
|
|
367 |
CMP.S R2, R1
|
|
|
368 |
BGT _dwbse
|
|
|
369 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
|
|
|
370 |
BARRIERS
|
|
|
371 |
|
|
|
372 |
MOVW R3, CPSR /* splx */
|
|
|
373 |
RET
|
|
|
374 |
|
|
|
375 |
TEXT cachedwbinv(SB), 1, $-4 /* D writeback+invalidate */
|
|
|
376 |
MOVW CPSR, R3 /* splhi */
|
|
|
377 |
ORR $(PsrDirq), R3, R1
|
|
|
378 |
MOVW R1, CPSR
|
|
|
379 |
|
|
|
380 |
BARRIERS /* force outstanding stores to cache */
|
|
|
381 |
/* keep writing back dirty cache lines until no more exist */
|
|
|
382 |
_dwbinv:
|
|
|
383 |
MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
|
|
|
384 |
BNE _dwbinv
|
|
|
385 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
|
|
|
386 |
BARRIERS
|
|
|
387 |
|
|
|
388 |
MOVW R3, CPSR /* splx */
|
|
|
389 |
RET
|
|
|
390 |
|
|
|
391 |
TEXT cachedwbinvse(SB), 1, $-4 /* D writeback+invalidate SE */
|
|
|
392 |
MOVW R0, R2 /* first arg: address */
|
|
|
393 |
|
|
|
394 |
MOVW CPSR, R3 /* splhi */
|
|
|
395 |
ORR $(PsrDirq), R3, R1
|
|
|
396 |
MOVW R1, CPSR
|
|
|
397 |
|
|
|
398 |
BARRIERS /* force outstanding stores to cache */
|
|
|
399 |
MOVW 4(FP), R1 /* second arg: size */
|
|
|
400 |
|
|
|
401 |
DSB
|
|
|
402 |
// CMP.S $(4*1024), R1
|
|
|
403 |
// BGT _dwbinv
|
|
|
404 |
ADD R2, R1
|
|
|
405 |
BIC $(CACHELINESZ-1), R2
|
|
|
406 |
_dwbinvse:
|
|
|
407 |
MCR CpSC, 0, R2, C(CpCACHE), C(CpCACHEwbi), CpCACHEse
|
|
|
408 |
ADD $CACHELINESZ, R2
|
|
|
409 |
CMP.S R2, R1
|
|
|
410 |
BGT _dwbinvse
|
|
|
411 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
|
|
|
412 |
BARRIERS
|
|
|
413 |
|
|
|
414 |
MOVW R3, CPSR /* splx */
|
|
|
415 |
RET
|
|
|
416 |
|
|
|
417 |
TEXT cachedinvse(SB), 1, $-4 /* D invalidate SE */
|
|
|
418 |
MOVW R0, R2 /* first arg: address */
|
|
|
419 |
|
|
|
420 |
MOVW CPSR, R3 /* splhi */
|
|
|
421 |
ORR $(PsrDirq), R3, R1
|
|
|
422 |
MOVW R1, CPSR
|
|
|
423 |
|
|
|
424 |
MOVW 4(FP), R1 /* second arg: size */
|
|
|
425 |
|
|
|
426 |
DSB
|
|
|
427 |
// CMP.S $(4*1024), R1
|
|
|
428 |
// BGT _dinv
|
|
|
429 |
ADD R2, R1
|
|
|
430 |
BIC $(CACHELINESZ-1), R2
|
|
|
431 |
_dinvse:
|
|
|
432 |
MCR CpSC, 0, R2, C(CpCACHE), C(CpCACHEinvd), CpCACHEse
|
|
|
433 |
ADD $CACHELINESZ, R2
|
|
|
434 |
CMP.S R2, R1
|
|
|
435 |
BGT _dinvse
|
|
|
436 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
|
|
|
437 |
BARRIERS
|
|
|
438 |
|
|
|
439 |
MOVW R3, CPSR /* splx */
|
|
|
440 |
RET
|
|
|
441 |
|
|
|
442 |
TEXT cacheuwbinv(SB), 1, $-4 /* D+I writeback+invalidate */
|
|
|
443 |
MOVW CPSR, R3 /* splhi */
|
|
|
444 |
ORR $(PsrDirq), R3, R1
|
|
|
445 |
MOVW R1, CPSR
|
|
|
446 |
|
|
|
447 |
BARRIERS /* force outstanding stores to cache */
|
|
|
448 |
/* keep writing back dirty cache lines until no more exist */
|
|
|
449 |
_uwbinv: /* D writeback+invalidate */
|
|
|
450 |
MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
|
|
|
451 |
BNE _uwbinv
|
|
|
452 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
|
|
|
453 |
BARRIERS
|
|
|
454 |
|
|
|
455 |
MOVW $0, R0 /* I invalidate */
|
|
|
456 |
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
|
|
|
457 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
|
|
|
458 |
BARRIERS
|
|
|
459 |
|
|
|
460 |
MOVW R3, CPSR /* splx */
|
|
|
461 |
RET
|
|
|
462 |
|
|
|
463 |
TEXT cacheiinv(SB), 1, $-4 /* I invalidate */
|
|
|
464 |
BARRIERS
|
|
|
465 |
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
|
|
|
466 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
|
|
|
467 |
BARRIERS
|
|
|
468 |
RET
|
|
|
469 |
|
|
|
470 |
TEXT cachedinv(SB), 1, $-4 /* D invalidate */
|
|
|
471 |
_dinv:
|
|
|
472 |
BARRIERS
|
|
|
473 |
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvd), CpCACHEall
|
|
|
474 |
/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
|
|
|
475 |
BARRIERS
|
|
|
476 |
RET
|
|
|
477 |
|
|
|
478 |
/*
|
|
|
479 |
* l2 cache
|
|
|
480 |
*
|
|
|
481 |
* these functions assume that the necessary l1 cache operations have been
|
|
|
482 |
* or will be done explicitly by the caller.
|
|
|
483 |
*/
|
|
|
484 |
|
|
|
485 |
/* enable l2 cache in config coproc. reg. do this while l1 caches are off. */
|
|
|
486 |
TEXT l2cachecfgon(SB), 1, $-4
|
|
|
487 |
BARRIERS
|
|
|
488 |
MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
|
|
|
489 |
BARRIERS
|
|
|
490 |
|
|
|
491 |
MRC CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
|
|
|
492 |
ORR $(CpTCl2ena | CpTCl2prefdis), R1 /* l2 on, prefetch off */
|
|
|
493 |
MCR CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
|
|
|
494 |
BARRIERS
|
|
|
495 |
RET
|
|
|
496 |
|
|
|
497 |
/* disable l2 cache in config coproc. reg. do this while l1 caches are off. */
|
|
|
498 |
TEXT l2cachecfgoff(SB), 1, $-4
|
|
|
499 |
BARRIERS
|
|
|
500 |
MRC CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
|
|
|
501 |
BIC $CpTCl2ena, R1
|
|
|
502 |
MCR CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
|
|
|
503 |
BARRIERS
|
|
|
504 |
|
|
|
505 |
MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
|
|
|
506 |
BARRIERS
|
|
|
507 |
RET
|
|
|
508 |
|
|
|
509 |
TEXT l2cacheuwb(SB), 1, $-4 /* L2 unified writeback */
|
|
|
510 |
MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
|
|
|
511 |
ISB
|
|
|
512 |
RET
|
|
|
513 |
|
|
|
514 |
TEXT l2cacheuwbse(SB), 1, $-4 /* L2 unified writeback SE */
|
|
|
515 |
MOVW R0, R2 /* first arg: address */
|
|
|
516 |
|
|
|
517 |
MOVW CPSR, R3 /* splhi */
|
|
|
518 |
ORR $(PsrDirq), R3, R1
|
|
|
519 |
MOVW R1, CPSR
|
|
|
520 |
|
|
|
521 |
MOVW 4(FP), R1 /* second arg: size */
|
|
|
522 |
|
|
|
523 |
ADD R2, R1
|
|
|
524 |
BIC $(CACHELINESZ-1), R2
|
|
|
525 |
_l2wbse:
|
|
|
526 |
MCR CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2flush), CpTCl2seva
|
|
|
527 |
ADD $CACHELINESZ, R2
|
|
|
528 |
CMP.S R2, R1
|
|
|
529 |
BGT _l2wbse
|
|
|
530 |
ISB
|
|
|
531 |
|
|
|
532 |
MOVW R3, CPSR /* splx */
|
|
|
533 |
RET
|
|
|
534 |
|
|
|
535 |
TEXT l2cacheuwbinv(SB), 1, $-4 /* L2 unified writeback+invalidate */
|
|
|
536 |
MOVW CPSR, R3 /* splhi */
|
|
|
537 |
ORR $(PsrDirq), R3, R1
|
|
|
538 |
MOVW R1, CPSR
|
|
|
539 |
|
|
|
540 |
MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
|
|
|
541 |
ISB
|
|
|
542 |
MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
|
|
|
543 |
ISB
|
|
|
544 |
|
|
|
545 |
MOVW R3, CPSR /* splx */
|
|
|
546 |
RET
|
|
|
547 |
|
|
|
548 |
TEXT l2cacheuwbinvse(SB), 1, $-4 /* L2 unified writeback+invalidate SE */
|
|
|
549 |
MOVW R0, R2 /* first arg: address */
|
|
|
550 |
|
|
|
551 |
MOVW CPSR, R3 /* splhi */
|
|
|
552 |
ORR $(PsrDirq), R3, R1
|
|
|
553 |
MOVW R1, CPSR
|
|
|
554 |
|
|
|
555 |
MOVW 4(FP), R1 /* second arg: size */
|
|
|
556 |
|
|
|
557 |
ADD R2, R1
|
|
|
558 |
BIC $(CACHELINESZ-1), R2
|
|
|
559 |
_l2wbinvse:
|
|
|
560 |
MCR CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2flush), CpTCl2seva
|
|
|
561 |
ISB
|
|
|
562 |
MCR CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2inv), CpTCl2seva
|
|
|
563 |
ADD $CACHELINESZ, R2
|
|
|
564 |
CMP.S R2, R1
|
|
|
565 |
BGT _l2wbinvse
|
|
|
566 |
ISB
|
|
|
567 |
|
|
|
568 |
MOVW R3, CPSR /* splx */
|
|
|
569 |
RET
|
|
|
570 |
|
|
|
571 |
TEXT l2cacheuinv(SB), 1, $-4 /* L2 unified invalidate */
|
|
|
572 |
MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
|
|
|
573 |
ISB
|
|
|
574 |
RET
|
|
|
575 |
|
|
|
576 |
TEXT l2cacheuinvse(SB), 1, $-4 /* L2 unified invalidate SE */
|
|
|
577 |
MOVW R0, R2 /* first arg: address */
|
|
|
578 |
|
|
|
579 |
MOVW CPSR, R3 /* splhi */
|
|
|
580 |
ORR $(PsrDirq), R3, R1
|
|
|
581 |
MOVW R1, CPSR
|
|
|
582 |
|
|
|
583 |
MOVW 4(FP), R1 /* second arg: size */
|
|
|
584 |
|
|
|
585 |
ADD R2, R1
|
|
|
586 |
BIC $(CACHELINESZ-1), R2
|
|
|
587 |
_l2invse:
|
|
|
588 |
MCR CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2inv), CpTCl2seva
|
|
|
589 |
ADD $CACHELINESZ, R2
|
|
|
590 |
CMP.S R2, R1
|
|
|
591 |
BGT _l2invse
|
|
|
592 |
ISB
|
|
|
593 |
|
|
|
594 |
MOVW R3, CPSR /* splx */
|
|
|
595 |
RET
|
|
|
596 |
|
|
|
597 |
/*
|
|
|
598 |
* enable mmu, i and d caches, and high vector
|
|
|
599 |
*/
|
|
|
600 |
TEXT mmuenable(SB), 1, $-4
|
|
|
601 |
MRC CpSC, 0, R0, C(CpCONTROL), C(0)
|
|
|
602 |
ORR $(CpChv|CpCmmu|CpCdcache|CpCicache|CpCwb|CpCsystem), R0
|
|
|
603 |
BIC $(CpCrom), R0
|
|
|
604 |
MCR CpSC, 0, R0, C(CpCONTROL), C(0)
|
|
|
605 |
BARRIERS
|
|
|
606 |
RET
|
|
|
607 |
|
|
|
608 |
TEXT mmudisable(SB), 1, $-4
|
|
|
609 |
MRC CpSC, 0, R0, C(CpCONTROL), C(0)
|
|
|
610 |
BIC $(CpChv|CpCmmu|CpCdcache|CpCicache|CpCwb), R0
|
|
|
611 |
MCR CpSC, 0, R0, C(CpCONTROL), C(0)
|
|
|
612 |
BARRIERS
|
|
|
613 |
RET
|
|
|
614 |
|
|
|
615 |
TEXT mmuinvalidate(SB), 1, $-4 /* invalidate all */
|
|
|
616 |
MOVW $0, R0
|
|
|
617 |
MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
|
|
|
618 |
BARRIERS
|
|
|
619 |
RET
|
|
|
620 |
|
|
|
621 |
TEXT mmuinvalidateaddr(SB), 1, $-4 /* invalidate single entry */
|
|
|
622 |
MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinvse
|
|
|
623 |
BARRIERS
|
|
|
624 |
RET
|
|
|
625 |
|
|
|
626 |
TEXT cpidget(SB), 1, $-4 /* main ID */
|
|
|
627 |
MRC CpSC, 0, R0, C(CpID), C(0), CpIDid
|
|
|
628 |
RET
|
|
|
629 |
|
|
|
630 |
TEXT cpctget(SB), 1, $-4 /* cache type */
|
|
|
631 |
MRC CpSC, 0, R0, C(CpID), C(0), CpIDct
|
|
|
632 |
RET
|
|
|
633 |
|
|
|
634 |
TEXT controlget(SB), 1, $-4 /* control */
|
|
|
635 |
MRC CpSC, 0, R0, C(CpCONTROL), C(0)
|
|
|
636 |
RET
|
|
|
637 |
|
|
|
638 |
TEXT ttbget(SB), 1, $-4 /* translation table base */
|
|
|
639 |
MRC CpSC, 0, R0, C(CpTTB), C(0)
|
|
|
640 |
RET
|
|
|
641 |
|
|
|
642 |
TEXT ttbput(SB), 1, $-4 /* translation table base */
|
|
|
643 |
MCR CpSC, 0, R0, C(CpTTB), C(0)
|
|
|
644 |
ISB
|
|
|
645 |
RET
|
|
|
646 |
|
|
|
647 |
TEXT dacget(SB), 1, $-4 /* domain access control */
|
|
|
648 |
MRC CpSC, 0, R0, C(CpDAC), C(0)
|
|
|
649 |
RET
|
|
|
650 |
|
|
|
651 |
TEXT dacput(SB), 1, $-4 /* domain access control */
|
|
|
652 |
MCR CpSC, 0, R0, C(CpDAC), C(0)
|
|
|
653 |
ISB
|
|
|
654 |
RET
|
|
|
655 |
|
|
|
656 |
TEXT fsrget(SB), 1, $-4 /* fault status */
|
|
|
657 |
MRC CpSC, 0, R0, C(CpFSR), C(0)
|
|
|
658 |
RET
|
|
|
659 |
|
|
|
660 |
TEXT farget(SB), 1, $-4 /* fault address */
|
|
|
661 |
MRC CpSC, 0, R0, C(CpFAR), C(0x0)
|
|
|
662 |
RET
|
|
|
663 |
|
|
|
664 |
TEXT pidget(SB), 1, $-4 /* address translation pid */
|
|
|
665 |
MRC CpSC, 0, R0, C(CpPID), C(0x0)
|
|
|
666 |
RET
|
|
|
667 |
|
|
|
668 |
TEXT pidput(SB), 1, $-4 /* address translation pid */
|
|
|
669 |
MCR CpSC, 0, R0, C(CpPID), C(0x0)
|
|
|
670 |
ISB
|
|
|
671 |
RET
|
|
|
672 |
|
|
|
673 |
TEXT splhi(SB), 1, $-4
|
|
|
674 |
MOVW $(MACHADDR+4), R2 /* save caller pc in Mach */
|
|
|
675 |
MOVW R14, 0(R2)
|
|
|
676 |
|
|
|
677 |
MOVW CPSR, R0 /* turn off interrupts */
|
|
|
678 |
ORR $(PsrDirq), R0, R1
|
|
|
679 |
MOVW R1, CPSR
|
|
|
680 |
RET
|
|
|
681 |
|
|
|
682 |
TEXT spllo(SB), 1, $-4
|
|
|
683 |
MOVW CPSR, R0
|
|
|
684 |
BIC $(PsrDirq), R0, R1
|
|
|
685 |
MOVW R1, CPSR
|
|
|
686 |
RET
|
|
|
687 |
|
|
|
688 |
TEXT splx(SB), 1, $-4
|
|
|
689 |
MOVW $(MACHADDR+0x04), R2 /* save caller pc in Mach */
|
|
|
690 |
MOVW R14, 0(R2)
|
|
|
691 |
|
|
|
692 |
MOVW R0, R1 /* reset interrupt level */
|
|
|
693 |
MOVW CPSR, R0
|
|
|
694 |
MOVW R1, CPSR
|
|
|
695 |
RET
|
|
|
696 |
|
|
|
697 |
TEXT splxpc(SB), 1, $-4 /* for iunlock */
|
|
|
698 |
MOVW R0, R1
|
|
|
699 |
MOVW CPSR, R0
|
|
|
700 |
MOVW R1, CPSR
|
|
|
701 |
RET
|
|
|
702 |
|
|
|
703 |
TEXT spldone(SB), 1, $0
|
|
|
704 |
RET
|
|
|
705 |
|
|
|
706 |
TEXT islo(SB), 1, $-4
|
|
|
707 |
MOVW CPSR, R0
|
|
|
708 |
AND $(PsrDirq), R0
|
|
|
709 |
EOR $(PsrDirq), R0
|
|
|
710 |
RET
|
|
|
711 |
|
|
|
712 |
TEXT splfhi(SB), $-4
|
|
|
713 |
MOVW CPSR, R0
|
|
|
714 |
ORR $(PsrDfiq|PsrDirq), R0, R1
|
|
|
715 |
MOVW R1, CPSR
|
|
|
716 |
RET
|
|
|
717 |
|
|
|
718 |
//TEXT splflo(SB), $-4
|
|
|
719 |
// MOVW CPSR, R0
|
|
|
720 |
// BIC $(PsrDfiq), R0, R1
|
|
|
721 |
// MOVW R1, CPSR
|
|
|
722 |
// RET
|
|
|
723 |
|
|
|
724 |
TEXT tas(SB), $-4
|
|
|
725 |
TEXT _tas(SB), $-4
|
|
|
726 |
MOVW R0,R1
|
|
|
727 |
MOVW $1,R0
|
|
|
728 |
SWPW R0,(R1) /* fix: deprecated in armv7 */
|
|
|
729 |
RET
|
|
|
730 |
|
|
|
731 |
//TEXT tas32(SB), 1, $-4
|
|
|
732 |
// MOVW R0, R1
|
|
|
733 |
// MOVW $0xDEADDEAD, R0
|
|
|
734 |
// MOVW R0, R3
|
|
|
735 |
// SWPW R0, (R1)
|
|
|
736 |
// CMP.S R0, R3
|
|
|
737 |
// BEQ _tasout
|
|
|
738 |
// EOR R3, R3 /* R3 = 0 */
|
|
|
739 |
// CMP.S R0, R3
|
|
|
740 |
// BEQ _tasout
|
|
|
741 |
// MOVW $1, R15 /* abort: lock != 0 && lock != $0xDEADDEAD */
|
|
|
742 |
//_tasout:
|
|
|
743 |
// RET
|
|
|
744 |
|
|
|
745 |
TEXT clz(SB), 1, $-4
|
|
|
746 |
CLZ(0, 0) /* 0 is R0 */
|
|
|
747 |
RET
|
|
|
748 |
|
|
|
749 |
TEXT setlabel(SB), 1, $-4
|
|
|
750 |
MOVW R13, 0(R0) /* sp */
|
|
|
751 |
MOVW R14, 4(R0) /* pc */
|
|
|
752 |
BARRIERS
|
|
|
753 |
MOVW $0, R0
|
|
|
754 |
RET
|
|
|
755 |
|
|
|
756 |
TEXT gotolabel(SB), 1, $-4
|
|
|
757 |
MOVW 0(R0), R13 /* sp */
|
|
|
758 |
MOVW 4(R0), R14 /* pc */
|
|
|
759 |
BARRIERS
|
|
|
760 |
MOVW $1, R0
|
|
|
761 |
RET
|
|
|
762 |
|
|
|
763 |
TEXT getcallerpc(SB), 1, $-4
|
|
|
764 |
MOVW 0(R13), R0
|
|
|
765 |
RET
|
|
|
766 |
|
|
|
767 |
TEXT _idlehands(SB), 1, $-4
|
|
|
768 |
MOVW CPSR, R3
|
|
|
769 |
// ORR $PsrDirq, R3, R1 /* splhi */
|
|
|
770 |
BIC $PsrDirq, R3, R1 /* spllo */
|
|
|
771 |
MOVW R1, CPSR
|
|
|
772 |
|
|
|
773 |
MOVW $0, R0 /* wait for interrupt */
|
|
|
774 |
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEintr), CpCACHEwait
|
|
|
775 |
ISB
|
|
|
776 |
|
|
|
777 |
MOVW R3, CPSR /* splx */
|
|
|
778 |
RET
|
|
|
779 |
|
|
|
780 |
TEXT barriers(SB), 1, $-4
|
|
|
781 |
BARRIERS
|
|
|
782 |
RET
|