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/*
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* omap3530 reboot code
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*
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* must fit in 11K to avoid stepping on PTEs; see mem.h.
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*
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* R11 is used by the loader as a temporary, so avoid it.
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*/
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#include "arm.s"
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/*
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* Turn off MMU, then copy the new kernel to its correct location
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* in physical memory. Then jump to the start of the kernel.
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*/
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/* main(PADDR(entry), PADDR(code), size); */
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TEXT main(SB), 1, $-4
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MOVW $setR12(SB), R12
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MOVW R0, p1+0(FP) /* destination, passed in R0 */
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MOVW CPSR, R0
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ORR $(PsrDirq|PsrDfiq), R0
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MOVW R0, CPSR /* splhi */
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BARRIERS
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PUTC('R')
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BIC $CpACasa, R1 /* no speculative I access forwarding to mem */
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/* slow down */
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ORR $(CpACcachenopipe|CpACcp15serial|CpACcp15waitidle|CpACcp15pipeflush), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
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BARRIERS
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BL cachesoff(SB)
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/* now back in 29- or 26-bit addressing, mainly for SB */
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/* double mapping of PHYSDRAM & KZERO now in effect */
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/*
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* turn the MMU off
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*/
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PUTC('e')
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/* first switch to PHYSDRAM-based addresses */
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DMB
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MOVW $KSEGM, R7 /* clear segment bits */
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MOVW $PHYSDRAM, R0 /* set dram base bits */
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BIC R7, R12 /* adjust SB */
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ORR R0, R12
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BL _r15warp(SB)
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/* don't care about saving R14; we're not returning */
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/*
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* now running in PHYSDRAM segment, not KZERO.
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*/
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PUTC('b')
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SUB $12, SP /* paranoia */
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BL cacheuwbinv(SB)
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ADD $12, SP /* paranoia */
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/* invalidate mmu mappings */
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MOVW $KZERO, R0 /* some valid virtual address */
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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PUTC('o')
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCmmu|CpCdcache|CpCicache), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0) /* mmu off */
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BARRIERS
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PUTC('o')
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/* copy in arguments from stack frame before moving stack */
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MOVW p2+4(FP), R4 /* phys source */
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MOVW n+8(FP), R5 /* byte count */
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MOVW p1+0(FP), R6 /* phys destination */
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/* set up a new stack for local vars and memmove args */
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MOVW R6, SP /* tiny trampoline stack */
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SUB $(0x20 + 4), SP /* back up before a.out header */
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// MOVW R14, -48(SP) /* store return addr */
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SUB $48, SP /* allocate stack frame */
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MOVW R5, 40(SP) /* save count */
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MOVW R6, 44(SP) /* save dest/entry */
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DELAY(printloop2, 2)
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PUTC('t')
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MOVW 40(SP), R5 /* restore count */
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MOVW 44(SP), R6 /* restore dest/entry */
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MOVW R6, 0(SP) /* normally saved LR goes here */
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MOVW R6, 4(SP) /* push dest */
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MOVW R6, R0
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MOVW R4, 8(SP) /* push src */
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MOVW R5, 12(SP) /* push size */
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BL memmove(SB)
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PUTC('-')
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/*
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* flush caches
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*/
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BL cacheuwbinv(SB)
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PUTC('>')
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DELAY(printloopret, 1)
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PUTC('\r')
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DELAY(printloopnl, 1)
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PUTC('\n')
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/*
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* jump to kernel entry point. Note the true kernel entry point is
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* the virtual address KZERO|R6, but this must wait until
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* the MMU is enabled by the kernel in l.s
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*/
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MOVW 44(SP), R6 /* restore R6 (dest/entry) */
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ORR R6, R6 /* NOP: avoid link bug */
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B (R6)
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PUTC('?')
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B 0(PC)
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/*
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* turn the caches off, double map PHYSDRAM & KZERO, invalidate TLBs, revert
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* to tiny addresses. upon return, it will be safe to turn off the mmu.
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*/
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TEXT cachesoff(SB), 1, $-4
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MOVM.DB.W [R14,R1-R10], (R13) /* save regs on stack */
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MOVW CPSR, R0
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ORR $(PsrDirq|PsrDfiq), R0
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MOVW R0, CPSR
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BARRIERS
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SUB $12, SP /* paranoia */
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BL cacheuwbinv(SB)
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ADD $12, SP /* paranoia */
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCicache|CpCdcache), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0) /* caches off */
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BARRIERS
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/*
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* caches are off
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*/
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/* invalidate stale TLBs before changing them */
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MOVW $KZERO, R0 /* some valid virtual address */
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* redo double map of PHYSDRAM, KZERO */
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MOVW $PHYSDRAM, R3
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CMP $KZERO, R3
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BEQ noun2map
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MOVW $(L1+L1X(PHYSDRAM)), R4 /* address of PHYSDRAM's PTE */
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $DOUBLEMAPMBS, R5
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_ptrdbl:
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ORR R3, R2, R1 /* first identity-map 0 to 0, etc. */
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MOVW R1, (R4)
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ADD $4, R4 /* bump PTE address */
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ADD $MiB, R3 /* bump pa */
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SUB.S $1, R5
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BNE _ptrdbl
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noun2map:
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/*
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* flush stale TLB entries
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*/
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BARRIERS
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MOVW $KZERO, R0 /* some valid virtual address */
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* switch back to PHYSDRAM addressing, mainly for SB */
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MOVW $KSEGM, R7 /* clear segment bits */
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MOVW $PHYSDRAM, R0 /* set dram base bits */
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BIC R7, R12 /* adjust SB */
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ORR R0, R12
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BIC R7, SP
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ORR R0, SP
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MOVM.IA.W (R13), [R14,R1-R10] /* restore regs from stack */
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MOVW $KSEGM, R0 /* clear segment bits */
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BIC R0, R14 /* adjust link */
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MOVW $PHYSDRAM, R0 /* set dram base bits */
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ORR R0, R14
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RET
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TEXT _r15warp(SB), 1, $-4
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BIC R7, R14 /* link */
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ORR R0, R14
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BIC R7, R13 /* SP */
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ORR R0, R13
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RET
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TEXT panic(SB), 1, $-4 /* stub */
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PUTC('?')
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RET
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TEXT pczeroseg(SB), 1, $-4 /* stub */
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RET
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#include "cache.v7.s"
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