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/*
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* mips 24k machine assist
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*/
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#undef MASK
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#define MASK(w) ((1<<(w))-1)
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#define SP R29
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#define NOP NOR R0, R0, R0
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#define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r
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/* a mips 24k erratum requires a NOP after; experience dictates EHB before */
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#define ERET EHB; WORD $0x42000018; NOP
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#define RETURN RET; NOP
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/*
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* R4000 instructions
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*/
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#define LL(base, rt) WORD $((060<<26)|((base)<<21)|((rt)<<16))
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#define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16))
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/* new instructions in mips 24k (mips32r2) */
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#define DI(rt) WORD $(0x41606000|((rt)<<16)) /* interrupts off */
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#define EI(rt) WORD $(0x41606020|((rt)<<16)) /* interrupts on */
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#define EHB WORD $0xc0
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/* jalr with hazard barrier, link in R22 */
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#define JALRHB(r) WORD $(((r)<<21)|(22<<11)|(1<<10)|9); NOP
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/* jump register with hazard barrier */
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#define JRHB(r) WORD $(((r)<<21)|(1<<10)|8); NOP
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#define MFC0(src,sel,dst) WORD $(0x40000000|((src)<<11)|((dst)<<16)|(sel))
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#define MTC0(src,dst,sel) WORD $(0x40800000|((dst)<<11)|((src)<<16)|(sel))
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#define MIPS24KNOP NOP /* for erratum #48 */
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#define RDHWR(hwr, r) WORD $(0x7c00003b|((hwr)<<11)|((r)<<16))
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#define SYNC WORD $0xf /* all sync barriers */
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#define WAIT WORD $0x42000020 /* wait for interrupt */
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/* all barriers, clears all hazards; clobbers r/Reg and R22 */
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#define BARRIERS(r, Reg, label) \
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SYNC; EHB; MOVW $ret(SB), Reg; JALRHB(r)
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/* same but return to KSEG1 */
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#define UBARRIERS(r, Reg, label) \
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SYNC; EHB; MOVW $ret(SB), Reg; OR $KSEG1, Reg; JALRHB(r)
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/* alternative definitions using labels */
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#ifdef notdef
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/* all barriers, clears all hazards; clobbers r/Reg */
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#define BARRIERS(r, Reg, label) \
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SYNC; EHB; \
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MOVW $label(SB), Reg; \
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JRHB(r); \
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TEXT label(SB), $-4; \
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NOP
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#define UBARRIERS(r, Reg, label) \
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SYNC; EHB; \
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MOVW $label(SB), Reg; \
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OR $KSEG1, Reg; \
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JRHB(r); \
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TEXT label(SB), $-4; \
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NOP
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#endif
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#define PUTC(c, r1, r2) CONST(PHYSCONS, r1); MOVW $(c), r2; MOVW r2, (r1); NOP
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/*
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* cache manipulation
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*/
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#define CACHE BREAK /* overloaded op-code */
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#define PI R((0 /* primary I cache */
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#define PD R((1 /* primary D cache */
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#define TD R((2 /* tertiary I/D cache */
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#define SD R((3 /* secondary combined I/D cache */
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#define IWBI (0<<2))) /* index write-back invalidate */
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#define ILT (1<<2))) /* index load tag */
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#define IST (2<<2))) /* index store tag */
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/* #define CDE (3<<2))) /* create dirty exclusive */
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#define HINV (4<<2))) /* hit invalidate */
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#define HWBI (5<<2))) /* hit write back invalidate */
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#define HWB (6<<2))) /* hit write back */
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/* #define HSV (7<<2))) /* hit set virtual */
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