WebSVN – planix.SVN – Blame – /os/branches/feature_fixcpp/sys/src/libmp/386/mpvecdigmulsub.s

Rev	Author	Line No.	Line
2	-	1	`/*`
		2	`* mpvecdigmulsub(mpdigit b, int n, mpdigit m, mpdigit p)`
		3	`*`
		4	`* p -= b*m`
		5	`*`
		6	`* each step look like:`
		7	`* hi,lo = m*b[i]`
		8	`* lo += oldhi + carry`
		9	`* hi += carry`
		10	`* p[i] += lo`
		11	`* oldhi = hi`
		12	`*`
		13	`* the registers are:`
		14	`* hi = DX - constrained by hardware`
		15	`* lo = AX - constrained by hardware`
		16	`* b = SI - can't be BP`
		17	`* p = DI - can't be BP`
		18	`* i = BP`
		19	`* n = CX - constrained by LOOP instr`
		20	`* m = BX`
		21	`* oldhi = EX`
		22	`*`
		23	`*/`
		24	`TEXT mpvecdigmulsub(SB),$4`
		25
		26	`MOVL b+0(FP),SI`
		27	`MOVL n+4(FP),CX`
		28	`MOVL m+8(FP),BX`
		29	`MOVL p+12(FP),DI`
		30	`XORL BP,BP`
		31	`MOVL BP,0(SP)`
		32	`_mulsubloop:`
		33	`MOVL (SI)(BP4),AX / lo = b[i] */`
		34	`MULL BX /* hi, lo = b[i] * m */`
		35	`ADDL 0(SP),AX /* lo += oldhi */`
33	7u83	36	`ADCL $0, DX /* hi += carry */`
2	-	37	`SUBL AX,(DI)(BP*4)`
33	7u83	38	`ADCL $0, DX /* hi += carry */`
2	-	39	`MOVL DX,0(SP)`
		40	`INCL BP`
		41	`LOOP _mulsubloop`
33	7u83	42	`MOVL CX, AX`
		43	`MOVL 0(SP),BX`
		44	`SUBL BX,(DI)(BP*4)`
		45	`SBBL CX, AX`
		46	`ORL $1, AX`
2	-	47	`RET`

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