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/*
2 
 * bcm2835 dma controller
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 *
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 * simplest to use only channels 0-6
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 *	channels 7-14 have reduced functionality
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 *	channel 15 is at a weird address
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 *	channels 0 and 15 have an "external 128 bit 8 word read FIFO"
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 *	  for memory to memory transfers
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 *
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 * Experiments show that only channels 2-5,11-12 work with mmc
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 */
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#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#define DMAREGS	(VIRTIO+0x7000)
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#define DBG	if(Dbg)
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enum {
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	Nchan		= 7,		/* number of dma channels */
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	Regsize		= 0x100,	/* size of regs for each chan */
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	Cbalign		= 32,		/* control block byte alignment */
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	Dbg		= 0,
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	/* registers for each dma controller */
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	Cs		= 0x00>>2,
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	Conblkad	= 0x04>>2,
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	Ti		= 0x08>>2,
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	Sourcead	= 0x0c>>2,
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	Destad		= 0x10>>2,
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	Txfrlen		= 0x14>>2,
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	Stride		= 0x18>>2,
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	Nextconbk	= 0x1c>>2,
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	Debug		= 0x20>>2,
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	/* collective registers */
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	Intstatus	= 0xfe0>>2,
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	Enable		= 0xff0>>2,
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	/* Cs */
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	Reset		= 1<<31,
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	Abort		= 1<<30,
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	Error		= 1<<8,
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	Waitwrite	= 1<<6,
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	Waitdreq	= 1<<5,
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	Paused		= 1<<4,
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	Dreq		= 1<<3,
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	Int		= 1<<2,
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	End		= 1<<1,
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	Active		= 1<<0,
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	/* Ti */
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	Permapshift= 16,
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	Srcignore	= 1<<11,
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	Srcdreq		= 1<<10,
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	Srcwidth128	= 1<<9,
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	Srcinc		= 1<<8,
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	Destignore	= 1<<7,
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	Destdreq	= 1<<6,
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	Destwidth128	= 1<<5,
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	Destinc		= 1<<4,
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	Waitresp	= 1<<3,
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	Tdmode		= 1<<1,
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	Inten		= 1<<0,
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	/* Debug */
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	Lite		= 1<<28,
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	Clrerrors	= 7<<0,
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};
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typedef struct Ctlr Ctlr;
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typedef struct Cb Cb;
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struct Ctlr {
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	u32int	*regs;
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	Cb	*cb;
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	Rendez	r;
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	int	dmadone;
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};
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struct Cb {
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	u32int	ti;
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	u32int	sourcead;
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	u32int	destad;
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	u32int	txfrlen;
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	u32int	stride;
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	u32int	nextconbk;
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	u32int	reserved[2];
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};
96 
 
97 
static Ctlr dma[Nchan];
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static u32int *dmaregs = (u32int*)DMAREGS;
99 
 
100 
static void
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dump(char *msg, uchar *p, int n)
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{
103 
	print("%s", msg);
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	while(n-- > 0)
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		print(" %2.2x", *p++);
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	print("\n");
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}
108 
 
109 
static void
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dumpdregs(char *msg, u32int *r)
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{
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	int i;
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114 
	print("%s: %#p =", msg, r);
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	for(i = 0; i < 9; i++)
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		print(" %8.8uX", r[i]);
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	print("\n");
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}
119 
 
120 
static int
121 
dmadone(void *a)
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{
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	return ((Ctlr*)a)->dmadone;
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}
125 
 
126 
static void
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dmainterrupt(Ureg*, void *a)
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{
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	Ctlr *ctlr;
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131 
	ctlr = a;
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	ctlr->regs[Cs] = Int;
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	ctlr->dmadone = 1;
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	wakeup(&ctlr->r);
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}
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137 
void
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dmastart(int chan, int dev, int dir, void *src, void *dst, int len)
139 
{
140 
	Ctlr *ctlr;
141 
	Cb *cb;
142 
	int ti;
143 
 
144 
	ctlr = &dma[chan];
145 
	if(ctlr->regs == nil){
146 
		ctlr->regs = (u32int*)(DMAREGS + chan*Regsize);
147 
		ctlr->cb = xspanalloc(sizeof(Cb), Cbalign, 0);
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		assert(ctlr->cb != nil);
149 
		dmaregs[Enable] |= 1<<chan;
150 
		ctlr->regs[Cs] = Reset;
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		while(ctlr->regs[Cs] & Reset)
152 
			;
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		intrenable(IRQDMA(chan), dmainterrupt, ctlr, 0, "dma");
154 
	}
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	cb = ctlr->cb;
156 
	ti = 0;
157 
	switch(dir){
158 
	case DmaD2M:
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		cachedwbinvse(dst, len);
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		ti = Srcdreq | Destinc;
161 
		cb->sourcead = DMAIO(src);
162 
		cb->destad = DMAADDR(dst);
163 
		break;
164 
	case DmaM2D:
165 
		cachedwbse(src, len);
166 
		ti = Destdreq | Srcinc;
167 
		cb->sourcead = DMAADDR(src);
168 
		cb->destad = DMAIO(dst);
169 
		break;
170 
	case DmaM2M:
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		cachedwbse(src, len);
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		cachedwbinvse(dst, len);
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		ti = Srcinc | Destinc;
174 
		cb->sourcead = DMAADDR(src);
175 
		cb->destad = DMAADDR(dst);
176 
		break;
177 
	}
178 
	cb->ti = ti | dev<<Permapshift | Inten;
179 
	cb->txfrlen = len;
180 
	cb->stride = 0;
181 
	cb->nextconbk = 0;
182 
	cachedwbse(cb, sizeof(Cb));
183 
	ctlr->regs[Cs] = 0;
184 
	microdelay(1);
185 
	ctlr->regs[Conblkad] = DMAADDR(cb);
186 
	DBG print("dma start: %ux %ux %ux %ux %ux %ux\n",
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		cb->ti, cb->sourcead, cb->destad, cb->txfrlen,
188 
		cb->stride, cb->nextconbk);
189 
	DBG print("intstatus %ux\n", dmaregs[Intstatus]);
190 
	dmaregs[Intstatus] = 0;
191 
	ctlr->regs[Cs] = Int;
192 
	microdelay(1);
193 
	coherence();
194 
	DBG dumpdregs("before Active", ctlr->regs);
195 
	ctlr->regs[Cs] = Active;
196 
	DBG dumpdregs("after Active", ctlr->regs);
197 
}
198 
 
199 
int
200 
dmawait(int chan)
201 
{
202 
	Ctlr *ctlr;
203 
	u32int *r;
204 
	int s;
205 
 
206 
	ctlr = &dma[chan];
207 
	tsleep(&ctlr->r, dmadone, ctlr, 3000);
208 
	ctlr->dmadone = 0;
209 
	r = ctlr->regs;
210 
	DBG dumpdregs("after sleep", r);
211 
	s = r[Cs];
212 
	if((s & (Active|End|Error)) != End){
213 
		print("dma chan %d %s Cs %ux Debug %ux\n", chan,
214 
			(s&End)? "error" : "timeout", s, r[Debug]);
215 
		r[Cs] = Reset;
216 
		r[Debug] = Clrerrors;
217 
		return -1;
218 
	}
219 
	r[Cs] = Int|End;
220 
	return 0;
221 
}