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/*
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* Here, we define everything that is specific for the blast board from Crawford Hill
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*/
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/* Clock speed of the blast board */
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#define CLKIN 72000000
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/*
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* Blast memory layout:
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* CS0: FE000000 -> FFFFFFFF (Flash)
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* CS1: FC000000 -> FCFFFFFF (DSP hpi)
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* CS2: 00000000 -> 03FFFFFF (60x sdram)
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* CS3: 04000000 -> 04FFFFFF (FPGA)
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* CS4: 05000000 -> 06FFFFFF (local bus sdram)
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* CS5: 07000000 -> 070FFFFF (eeprom - not populated)
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* CS6: E0000000 -> E0FFFFFF (FPGA)
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*
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* Main Board memory lay out:
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* CS0: FE000000 -> FEFFFFFF (16 M FLASH)
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* CS1: FC000000 -> FCFFFFFF (16 M DSP1)
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* CS2: 00000000 -> 03FFFFFF (64 M SDRAM)
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* CS3: 04000000 -> 04FFFFFF (16M DSP2)
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* CS4: 05000000 -> 06FFFFFF (32 M Local SDRAM)
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* CS5: 07000000 -> 070FFFFF (eeprom - not populated)
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* CS6: E0000000 -> E0FFFFFF (16 M FPGA)
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*
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* CS2, CS3, CS4, (and CS5) are covered by DBAT 0, CS0 and CS1 by DBAT 3, CS6 by DBAT 2
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*/
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#define IMMR 0xf0000000
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#define FLASHMEM 0xfe000000
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#define FLASHSIZE 0x01000000
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#define DSP1BASE 0xfc000000
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#define DSP1SIZE 0x01000000
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#define MEM1BASE 0x00000000
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#define MEM1SIZE 0x04000000
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#define DSP2BASE 0x04000000
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#define DSP2SIZE 0x01000000
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#define MEM2BASE 0x05000000
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/* #define MEM2SIZE 0x02000000 */
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#define MEM2SIZE 0
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#define FPGABASE 0xe0000000
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#define FPGASIZE 0x01000000
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#define PLAN9INI 0x00460000
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#define TLBENTRIES 32
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/*
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* PTE bits for fault.c. These belong to the second PTE word. Validity is
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* implied for putmmu(), and we always set PTE0_V. PTEVALID is used
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* here to set cache policy bits on a global basis.
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*/
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#define PTEVALID PTE1_M
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#define PTEWRITE (PTE1_RW|PTE1_C)
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#define PTERONLY PTE1_RO
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#define PTEUNCACHED PTE1_I
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/* SMC Uart configuration */
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#define SMC1PORT 3 /* Port D */
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#define SMTXD1 BIT(9)
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#define SMRXD1 BIT(8)
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/* Ethernet FCC configuration */
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#define A1txer 0x00000004
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#define A1rxdv 0x00000010
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#define A1txen 0x00000008
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#define A1rxer 0x00000020
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#define A1col 0x00000001
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#define A1crs 0x00000002
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#define A1txdat 0x00003c00
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#define A1rxdat 0x0003c000
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#define B2txer 0x00000001
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#define B2rxdv 0x00000002
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#define B2txen 0x00000004
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#define B2rxer 0x00000008
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#define B2col 0x00000010
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#define B2crs 0x00000020
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#define B2txdat 0x000003c0
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#define B2rxdat 0x00003c00
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#define B3rxdv 0x00004000
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#define B3rxer 0x00008000
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#define B3txer 0x00010000
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#define B3txen 0x00020000
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#define B3col 0x00040000
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#define B3crs 0x00080000
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#define B3txdat 0x0f000000
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#define B3rxdat 0x00f00000
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#define A1psor0 (A1rxdat | A1txdat)
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#define A1psor1 (A1col | A1crs | A1txer | A1txen | A1rxdv | A1rxer)
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#define A1dir0 (A1rxdat | A1crs | A1col | A1rxer | A1rxdv)
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#define A1dir1 (A1txdat | A1txen | A1txer)
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#define B2psor0 (B2rxdat | B2txdat | B2crs | B2col | B2rxer | B2rxdv | B2txer)
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#define B2psor1 (B2txen)
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#define B2dir0 (B2rxdat | B2crs | B2col | B2rxer | B2rxdv)
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#define B2dir1 (B2txdat | B2txen | B2txer)
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#define B3psor0 (B3rxdat | B3txdat | B3crs | B3col | B3rxer | B3rxdv | B3txer | B3txen)
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#define B3psor1 0
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#define B3dir0 (B3rxdat | B3crs | B3col | B3rxer | B3rxdv)
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#define B3dir1 (B3txdat | B3txen | B3txer)
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