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/*
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* nvidia tegra 2 machine assist, definitions
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* dual-core cortex-a9 processor
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*
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* R9 and R10 are used for `extern register' variables.
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* R11 is used by the loader as a temporary, so avoid it.
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*/
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#include "mem.h"
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#include "arm.h"
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#undef B /* B is for 'botch' */
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#define KADDR(pa) (KZERO | ((pa) & ~KSEGM))
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#define PADDR(va) (PHYSDRAM | ((va) & ~KSEGM))
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#define L1X(va) (((((va))>>20) & 0x0fff)<<2)
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#define MACHADDR (L1-MACHSIZE) /* only room for cpu0's */
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/* L1 pte values */
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#define PTEDRAM (Dom0|L1AP(Krw)|Section|L1ptedramattrs)
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#define PTEIO (Dom0|L1AP(Krw)|Section)
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#define DOUBLEMAPMBS 512 /* megabytes of low dram to double-map */
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/* steps on R0 */
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#define DELAY(label, mloops) \
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MOVW $((mloops)*1000000), R0; \
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label: \
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SUB.S $1, R0; \
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BNE label
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/* print a byte on the serial console; clobbers R0 & R6; needs R12 (SB) set */
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#define PUTC(c) \
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BARRIERS; \
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MOVW $(c), R0; \
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MOVW $PHYSCONS, R6; \
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MOVW R0, (R6); \
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BARRIERS
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/*
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* new instructions
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*/
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#define SMC WORD $0xe1600070 /* low 4-bits are call # (trustzone) */
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/* flush branch-target cache */
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#define FLBTC MTCP CpSC, 0, PC, C(CpCACHE), C(CpCACHEinvi), CpCACHEflushbtc
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/* flush one entry of the branch-target cache, va in R0 (cortex) */
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#define FLBTSE MTCP CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEflushbtse
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/* arm v7 arch defines these */
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#define DSB WORD $0xf57ff04f /* data synch. barrier; last f = SY */
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#define DMB WORD $0xf57ff05f /* data mem. barrier; last f = SY */
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#define ISB WORD $0xf57ff06f /* instr. sync. barrier; last f = SY */
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#define WFI WORD $0xe320f003 /* wait for interrupt */
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#define NOOP WORD $0xe320f000
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#define CLZ(s, d) WORD $(0xe16f0f10 | (d) << 12 | (s)) /* count leading 0s */
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#define SETEND(o) WORD $(0xf1010000 | (o) << 9) /* o==0, little-endian */
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#define CPSIE WORD $0xf1080080 /* intr enable: zeroes I bit */
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#define CPSID WORD $0xf10c00c0 /* intr disable: sets I,F bits */
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#define CPSAE WORD $0xf1080100 /* async abt enable: zeroes A bit */
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#define CPSMODE(m) WORD $(0xf1020000 | (m)) /* switch to mode m (PsrM*) */
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#define CLREX WORD $0xf57ff01f
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/* floating point */
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#define VMRS(fp, cpu) WORD $(0xeef00a10 | (fp)<<16 | (cpu)<<12) /* FP → arm */
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#define VMSR(cpu, fp) WORD $(0xeee00a10 | (fp)<<16 | (cpu)<<12) /* arm → FP */
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/*
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* a popular code sequence used to write a pte for va is:
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*
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* MOVW R(n), TTB[LnX(va)]
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* // clean the cache line
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* DSB
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* // invalidate tlb entry for va
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* FLBTC
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* DSB
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* PFF (now ISB)
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*/
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#define BARRIERS FLBTC; DSB; ISB
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/*
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* invoked with PTE bits in R2, pa in R3, PTE pointed to by R4.
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* fill PTE pointed to by R4 and increment R4 past it.
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* increment R3 by a MB. clobbers R1.
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*/
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#define FILLPTE() \
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ORR R3, R2, R1; /* pte bits in R2, pa in R3 */ \
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MOVW R1, (R4); \
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ADD $4, R4; /* bump PTE address */ \
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ADD $MiB, R3; /* bump pa */ \
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/* zero PTE pointed to by R4 and increment R4 past it. assumes R0 is 0. */
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#define ZEROPTE() \
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MOVW R0, (R4); \
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ADD $4, R4; /* bump PTE address */
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/*
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* set kernel SB for zero segment (instead of usual KZERO segment).
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* NB: the next line puts rubbish in R12:
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* MOVW $setR12-KZERO(SB), R12
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*/
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#define SETZSB \
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MOVW $setR12(SB), R12; /* load kernel's SB */ \
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SUB $KZERO, R12; \
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ADD $PHYSDRAM, R12
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/*
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* note that 5a's RFE is not the v6/7 arch. instruction (0xf8900a00),
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* which loads CPSR from the word after the PC at (R13), but rather
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* the pre-v6 simulation `MOVM.IA.S.W (R13), [R15]' (0xe8fd8000 since
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* MOVM is LDM in this case), which loads CPSR not from memory but
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* from SPSR due to `.S'.
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*/
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#define RFEV7(r) WORD $(0xf8900a00 | (r) << 16)
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#define RFEV7W(r) WORD $(0xf8900a00 | (r) << 16 | 0x00200000) /* RFE.W */
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#define RFEV7DB(r) WORD $(0xf9100a00 | (r) << 16) /* RFE.DB */
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#define RFEV7DBW(r) WORD $(0xf9100a00 | (r) << 16 | 0x00200000) /* RFE.DB.W */
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#define CKPSR(psr, tmp, bad)
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#define CKCPSR(psrtmp, tmp, bad)
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/* return with cpu id in r and condition codes set from "r == 0" */
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#define CPUID(r) \
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MFCP CpSC, 0, r, C(CpID), C(CpIDidct), CpIDmpid; \
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AND.S $(MAXMACH-1), r /* mask out non-cpu-id bits */
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