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/*
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* arm exception handlers
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*/
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#include "arm.s"
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#undef B /* B is for 'botch' */
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/*
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* exception vectors, copied by trapinit() to somewhere useful
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*/
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TEXT vectors(SB), 1, $-4
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MOVW 0x18(R15), R15 /* reset */
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MOVW 0x18(R15), R15 /* undefined instr. */
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MOVW 0x18(R15), R15 /* SWI & SMC */
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MOVW 0x18(R15), R15 /* prefetch abort */
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MOVW 0x18(R15), R15 /* data abort */
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MOVW 0x18(R15), R15 /* hypervisor call */
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MOVW 0x18(R15), R15 /* IRQ */
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MOVW 0x18(R15), R15 /* FIQ */
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TEXT vtable(SB), 1, $-4
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WORD $_vrst-KZERO(SB) /* reset, in svc mode already */
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WORD $_vund(SB) /* undefined, switch to svc mode */
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WORD $_vsvc(SB) /* swi, in svc mode already */
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WORD $_vpabt(SB) /* prefetch abort, switch to svc mode */
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WORD $_vdabt(SB) /* data abort, switch to svc mode */
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WORD $_vhype(SB) /* hypervisor call */
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WORD $_virq(SB) /* IRQ, switch to svc mode */
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WORD $_vfiq(SB) /* FIQ, switch to svc mode */
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/*
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* reset - start additional cpus
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*/
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TEXT _vrst(SB), 1, $-4
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/* running in the zero segment (pc is lower 256MB) */
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CPSMODE(PsrMsvc) /* should be redundant */
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CPSID
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CPSAE
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SETEND(0) /* force little-endian */
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BARRIERS
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SETZSB
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MOVW $PsrMsvc, SPSR
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MOVW $0, R14
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/* invalidate i-cache and branch-target cache */
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MTCP CpSC, 0, PC, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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BARRIERS
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BL cpureset(SB)
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spin:
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B spin
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/*
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* system call
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*/
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TEXT _vsvc(SB), 1, $-4 /* SWI */
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CLREX
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BARRIERS
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/* stack is m->stack */
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MOVW.W R14, -4(R13) /* ureg->pc = interrupted PC */
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MOVW SPSR, R14 /* ureg->psr = SPSR */
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MOVW.W R14, -4(R13) /* ... */
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MOVW $PsrMsvc, R14 /* ureg->type = PsrMsvc */
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MOVW.W R14, -4(R13) /* ... */
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/* avoid the ambiguity described in notes/movm.w. */
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MOVM.DB.S [R0-R14], (R13) /* save user level registers */
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SUB $(NREGS*4), R13 /* r13 now points to ureg */
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MOVW $setR12(SB), R12 /* Make sure we've got the kernel's SB loaded */
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/*
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* set up m and up registers since user registers could contain anything
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*/
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CPUID(R1)
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SLL $2, R1 /* convert to word index */
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MOVW $machaddr(SB), R2
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ADD R1, R2
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MOVW (R2), R(MACH) /* m = machaddr[cpuid] */
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CMP $0, R(MACH)
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MOVW.EQ $MACHADDR, R0 /* paranoia: use MACHADDR if 0 */
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MOVW 8(R(MACH)), R(USER) /* up = m->proc */
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MOVW ((NREGS+1)*4)(R13), R2 /* saved SPSR (user mode) */
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MOVW R13, R0 /* first arg is pointer to ureg */
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SUB $8, R13 /* space for argument+link */
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BL syscall(SB)
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/*
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* caller saves on plan 9, so registers other than 9, 10, 13 & 14
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* may have been trashed when we get here.
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*/
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MOVW $setR12(SB), R12 /* reload kernel's SB */
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ADD $(8+4*NREGS), R13 /* make r13 point to ureg->type */
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MOVW 8(R13), R14 /* restore link */
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MOVW 4(R13), R0 /* restore SPSR */
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/*
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* return from user-mode exception.
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* expects new SPSR in R0. R13 must point to ureg->type.
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*/
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_rfue:
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TEXT rfue(SB), 1, $-4
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MOVW R0, SPSR /* ... */
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/*
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* order on stack is type, psr, pc, but RFEV7 needs pc, psr.
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* step on type and previous word to hold temporary values.
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* we could instead change the order in which psr & pc are pushed.
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*/
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MOVW 4(R13), R1 /* psr */
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MOVW 8(R13), R2 /* pc */
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MOVW R2, 4(R13) /* pc */
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MOVW R1, 8(R13) /* psr */
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MOVM.DB.S (R13), [R0-R14] /* restore user registers */
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ADD $4, R13 /* pop type, sp -> pc */
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RFEV7W(13)
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TEXT _vund(SB), 1, $-4 /* undefined */
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/* sp is m->sund */
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MOVM.IA [R0-R4], (R13) /* free some working space */
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MOVW $PsrMund, R0
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B _vswitch
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TEXT _vpabt(SB), 1, $-4 /* prefetch abort */
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/* sp is m->sabt */
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MOVM.IA [R0-R4], (R13) /* free some working space */
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MOVW $PsrMabt, R0 /* r0 = type */
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B _vswitch
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TEXT _vdabt(SB), 1, $-4 /* data abort */
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/* sp is m->sabt */
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MOVM.IA [R0-R4], (R13) /* free some working space */
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MOVW $(PsrMabt+1), R0 /* r0 = type */
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B _vswitch
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TEXT _virq(SB), 1, $-4 /* IRQ */
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/* sp is m->sirq */
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MOVM.IA [R0-R4], (R13) /* free some working space */
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MOVW $PsrMirq, R0 /* r0 = type */
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B _vswitch
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/*
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* come here with type in R0 and R13 pointing above saved [r0-r4].
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* we'll switch to SVC mode and then call trap.
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*/
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_vswitch:
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// TEXT _vswtch(SB), 1, $-4 /* make symbol visible to debuggers */
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CLREX
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BARRIERS
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MOVW SPSR, R1 /* save SPSR for ureg */
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/*
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* R12 needs to be set before using PsrMbz, so BIGENDCHECK code has
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* been moved below.
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*/
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MOVW R14, R2 /* save interrupted pc for ureg */
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MOVW R13, R3 /* save pointer to where the original [R0-R4] are */
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/*
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* switch processor to svc mode. this switches the banked registers
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* (r13 [sp] and r14 [link]) to those of svc mode (so we must be sure
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* to never get here already in svc mode).
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*/
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CPSMODE(PsrMsvc) /* switch! */
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CPSID
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AND.S $0xf, R1, R4 /* interrupted code kernel or user? */
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BEQ _userexcep
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/*
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* here for trap from SVC mode
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*/
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/* push ureg->{type, psr, pc} onto Msvc stack.
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* r13 points to ureg->type after.
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*/
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MOVM.DB.W [R0-R2], (R13)
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MOVM.IA (R3), [R0-R4] /* restore [R0-R4] from previous mode's stack */
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/*
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* avoid the ambiguity described in notes/movm.w.
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* In order to get a predictable value in R13 after the stores,
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* separate the store-multiple from the stack-pointer adjustment.
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* We'll assume that the old value of R13 should be stored on the stack.
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*/
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/* save kernel level registers, at end r13 points to ureg */
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MOVM.DB [R0-R14], (R13)
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SUB $(NREGS*4), R13 /* SP now points to saved R0 */
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MOVW $setR12(SB), R12 /* Make sure we've got the kernel's SB loaded */
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/* previous mode was svc, so the saved spsr should be sane. */
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MOVW ((NREGS+1)*4)(R13), R1
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MOVM.IA (R13), [R0-R8] /* restore a few user registers */
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MOVW R13, R0 /* first arg is pointer to ureg */
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SUB $(4*2), R13 /* space for argument+link (for debugger) */
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MOVW $0xdeaddead, R11 /* marker */
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BL trap(SB) /* trap(ureg) */
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/*
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* caller saves on plan 9, so registers other than 9, 10, 13 & 14
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* may have been trashed when we get here.
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*/
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MOVW $setR12(SB), R12 /* reload kernel's SB */
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ADD $(4*2+4*NREGS), R13 /* make r13 point to ureg->type */
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/*
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* if we interrupted a previous trap's handler and are now
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* returning to it, we need to propagate the current R(MACH) (R10)
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* by overriding the saved one on the stack, since we may have
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* been rescheduled and be on a different processor now than
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* at entry.
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*/
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MOVW R(MACH), (-(NREGS-MACH)*4)(R13) /* restore current cpu's MACH */
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MOVW 8(R13), R14 /* restore link */
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MOVW 4(R13), R0 /* restore SPSR */
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/* return from kernel-mode exception */
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MOVW R0, SPSR /* ... */
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/*
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* order on stack is type, psr, pc, but RFEV7 needs pc, psr.
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* step on type and previous word to hold temporary values.
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* we could instead change the order in which psr & pc are pushed.
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*/
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MOVW 4(R13), R1 /* psr */
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MOVW 8(R13), R2 /* pc */
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MOVW R2, 4(R13) /* pc */
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MOVW R1, 8(R13) /* psr */
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/* restore kernel regs other than SP; we're using it */
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SUB $(NREGS*4), R13
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MOVM.IA.W (R13), [R0-R12]
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ADD $4, R13 /* skip saved kernel SP */
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MOVM.IA.W (R13), [R14]
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ADD $4, R13 /* pop type, sp -> pc */
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BARRIERS
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RFEV7W(13)
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/*
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* here for trap from USER mode
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*/
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_userexcep:
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MOVM.DB.W [R0-R2], (R13) /* set ureg->{type, psr, pc}; r13 points to ureg->type */
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MOVM.IA (R3), [R0-R4] /* restore [R0-R4] from previous mode's stack */
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255 |
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/* avoid the ambiguity described in notes/movm.w. */
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MOVM.DB.S [R0-R14], (R13) /* save kernel level registers */
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SUB $(NREGS*4), R13 /* r13 now points to ureg */
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259 |
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MOVW $setR12(SB), R12 /* Make sure we've got the kernel's SB loaded */
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261 |
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/*
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* set up m and up registers since user registers could contain anything
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*/
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CPUID(R1)
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SLL $2, R1 /* convert to word index */
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MOVW $machaddr(SB), R2
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ADD R1, R2
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MOVW (R2), R(MACH) /* m = machaddr[cpuid] */
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CMP $0, R(MACH)
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MOVW.EQ $MACHADDR, R0 /* paranoia: use MACHADDR if 0 */
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MOVW 8(R(MACH)), R(USER) /* up = m->proc */
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273 |
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MOVW ((NREGS+1)*4)(R13), R2 /* saved SPSR */
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275 |
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MOVW R13, R0 /* first arg is pointer to ureg */
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SUB $(4*2), R13 /* space for argument+link (for debugger) */
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278 |
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279 |
BL trap(SB) /* trap(ureg) */
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/*
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* caller saves on plan 9, so registers other than 9, 10, 13 & 14
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* may have been trashed when we get here.
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*/
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284 |
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285 |
ADD $(4*2+4*NREGS), R13 /* make r13 point to ureg->type */
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286 |
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287 |
MOVW 8(R13), R14 /* restore link */
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288 |
MOVW 4(R13), R0 /* restore SPSR */
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289 |
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290 |
MOVW 4(R13), R0 /* restore SPSR */
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B _rfue
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292 |
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293 |
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294 |
TEXT _vfiq(SB), 1, $-4 /* FIQ */
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295 |
PUTC('?')
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296 |
PUTC('f')
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297 |
PUTC('i')
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298 |
PUTC('q')
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299 |
RFE /* FIQ is special, ignore it for now */
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300 |
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301 |
TEXT _vhype(SB), 1, $-4
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302 |
PUTC('?')
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303 |
PUTC('h')
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304 |
PUTC('y')
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305 |
PUTC('p')
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306 |
RFE
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307 |
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308 |
/*
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309 |
* set the stack value for the mode passed in R0
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310 |
*/
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311 |
TEXT setr13(SB), 1, $-4
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312 |
MOVW 4(FP), R1
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313 |
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314 |
MOVW CPSR, R2
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315 |
BIC $(PsrMask|PsrMbz), R2, R3
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316 |
ORR $(PsrDirq|PsrDfiq), R3
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317 |
ORR R0, R3
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318 |
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319 |
MOVW R3, CPSR /* switch to new mode */
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320 |
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321 |
MOVW R13, R0 /* return old sp */
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322 |
MOVW R1, R13 /* install new one */
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323 |
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324 |
MOVW R2, CPSR /* switch back to old mode */
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325 |
RET
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