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1 |
/*
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2 |
* Generic VGA registers.
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*/
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4 |
enum {
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5 |
MiscW = 0x03C2, /* Miscellaneous Output (W) */
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6 |
MiscR = 0x03CC, /* Miscellaneous Output (R) */
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7 |
Status0 = 0x03C2, /* Input status 0 (R) */
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8 |
Status1 = 0x03DA, /* Input Status 1 (R) */
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9 |
FeatureR = 0x03CA, /* Feature Control (R) */
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10 |
FeatureW = 0x03DA, /* Feature Control (W) */
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11 |
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12 |
Seqx = 0x03C4, /* Sequencer Index, Data at Seqx+1 */
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13 |
Crtx = 0x03D4, /* CRT Controller Index, Data at Crtx+1 */
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14 |
Grx = 0x03CE, /* Graphics Controller Index, Data at Grx+1 */
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15 |
Attrx = 0x03C0, /* Attribute Controller Index and Data */
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16 |
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17 |
PaddrW = 0x03C8, /* Palette Address Register, write */
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18 |
Pdata = 0x03C9, /* Palette Data Register */
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19 |
Pixmask = 0x03C6, /* Pixel Mask Register */
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20 |
PaddrR = 0x03C7, /* Palette Address Register, read */
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21 |
Pstatus = 0x03C7, /* DAC Status (RO) */
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22 |
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23 |
Pcolours = 256, /* Palette */
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24 |
Red = 0,
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25 |
Green = 1,
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26 |
Blue = 2,
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27 |
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28 |
Pblack = 0x00,
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29 |
Pwhite = 0xFF,
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30 |
};
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31 |
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32 |
enum {
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33 |
RefFreq = 14318180, /* External Reference Clock frequency */
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34 |
VgaFreq0 = 25175000,
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35 |
VgaFreq1 = 28322000,
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};
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37 |
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enum {
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Namelen = 32,
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};
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41 |
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typedef struct Ctlr Ctlr;
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typedef struct Vga Vga;
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44 |
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typedef struct Ctlr {
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char name[Namelen+1];
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void (*snarf)(Vga*, Ctlr*);
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48 |
void (*options)(Vga*, Ctlr*);
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49 |
void (*init)(Vga*, Ctlr*);
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50 |
void (*load)(Vga*, Ctlr*);
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void (*dump)(Vga*, Ctlr*);
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char* type;
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ulong flag;
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Ctlr* link;
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} Ctlr;
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58 |
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enum { /* flag */
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Fsnarf = 0x00000001, /* snarf done */
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Foptions = 0x00000002, /* options done */
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Finit = 0x00000004, /* init done */
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Fload = 0x00000008, /* load done */
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Fdump = 0x00000010, /* dump done */
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Ferror = 0x00000020, /* error during snarf */
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66 |
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67 |
Hpclk2x8 = 0x00000100, /* have double 8-bit mode */
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68 |
Upclk2x8 = 0x00000200, /* use double 8-bit mode */
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Henhanced = 0x00000400, /* have enhanced mode */
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70 |
Uenhanced = 0x00000800, /* use enhanced mode */
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71 |
Hpvram = 0x00001000, /* have parallel VRAM */
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72 |
Upvram = 0x00002000, /* use parallel VRAM */
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Hextsid = 0x00004000, /* have external SID mode */
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Uextsid = 0x00008000, /* use external SID mode */
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Hclk2 = 0x00010000, /* have clock-doubler */
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Uclk2 = 0x00020000, /* use clock-doubler */
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Hlinear = 0x00040000, /* have linear-address mode */
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Ulinear = 0x00080000, /* use linear-address mode */
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Hclkdiv = 0x00100000, /* have a clock-divisor */
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Uclkdiv = 0x00200000, /* use clock-divisor */
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Hsid32 = 0x00400000, /* have a 32-bit (as opposed to 64-bit) SID */
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};
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typedef struct Attr Attr;
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typedef struct Attr {
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char* attr;
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char* val;
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Attr* next;
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} Attr;
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typedef struct Mode {
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char type[Namelen+1]; /* monitor type e.g. "vs1782" */
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char size[Namelen+1]; /* size e.g. "1376x1024x8" */
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char chan[Namelen+1]; /* channel descriptor, e.g. "m8" or "r8g8b8a8" */
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char name[Namelen+1]; /* optional */
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int frequency; /* Dot Clock (MHz) */
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int deffrequency; /* Default dot clock if calculation can't be done */
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int x; /* Horizontal Display End (Crt01), from .size[] */
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int y; /* Vertical Display End (Crt18), from .size[] */
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102 |
int z; /* depth, from .size[] */
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103 |
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104 |
int ht; /* Horizontal Total (Crt00) */
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int shb; /* Start Horizontal Blank (Crt02) */
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int ehb; /* End Horizontal Blank (Crt03) */
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107 |
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108 |
int shs; /* optional Start Horizontal Sync (Crt04) */
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109 |
int ehs; /* optional End Horizontal Sync (Crt05) */
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110 |
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111 |
int vt; /* Vertical Total (Crt06) */
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int vrs; /* Vertical Retrace Start (Crt10) */
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113 |
int vre; /* Vertical Retrace End (Crt11) */
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114 |
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int vbs; /* optional Vertical Blank Start */
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116 |
int vbe; /* optional Vertical Blank End */
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117 |
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118 |
ulong videobw;
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119 |
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char hsync;
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char vsync;
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char interlace;
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123 |
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Attr* attr;
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} Mode;
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126 |
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/*
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* The sizes of the register sets are large as many SVGA and GUI chips have extras.
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* The Crt registers are ushorts in order to keep overflow bits handy.
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* The clock elements are used for communication between the VGA, RAMDAC and clock chips;
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* they can use them however they like, it's assumed they will be used compatibly.
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*
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* The mode->x, mode->y coordinates are the physical size of the screen.
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* Virtx and virty are the coordinates of the underlying memory image.
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* This can be used to implement panning around a larger screen or to cope
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* with chipsets that need the in-memory pixel line width to be a round number.
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* For example, virge.c uses this because the Savage chipset needs the pixel
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* width to be a multiple of 16. Also, mga2164w.c needs the pixel width
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* to be a multiple of 128.
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*
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* Vga->panning differentiates between these two uses of virtx, virty.
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*
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* (14 October 2001, rsc) Most drivers don't know the difference between
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* mode->x and virtx, a bug that should be corrected. Vga.c, virge.c, and
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* mga2164w.c know. For the others, the computation that sets crt[0x13]
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* should use virtx instead of mode->x (and maybe other places change too,
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* dependent on the driver).
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*/
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typedef struct Vga {
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uchar misc;
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uchar feature;
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uchar sequencer[256];
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ushort crt[256];
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uchar graphics[256];
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uchar attribute[256];
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uchar pixmask;
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uchar pstatus;
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158 |
uchar palette[Pcolours][3];
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159 |
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160 |
ulong f[2]; /* clock */
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ulong d[2];
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ulong i[2];
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ulong m[2];
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ulong n[2];
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ulong p[2];
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ulong q[2];
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ulong r[2];
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168 |
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ulong vma; /* video memory linear-address alignment */
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ulong vmb; /* video memory linear-address base */
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ulong apz; /* aperture size */
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ulong vmz; /* video memory size */
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173 |
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ulong membw; /* memory bandwidth, MB/s */
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175 |
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176 |
long offset; /* BIOS string offset */
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char* bios; /* matching BIOS string */
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Pcidev* pci; /* matching PCI device if any */
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179 |
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Mode* mode;
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181 |
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182 |
ulong virtx; /* resolution of virtual screen */
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183 |
ulong virty;
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184 |
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int panning; /* pan the virtual screen */
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186 |
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187 |
Ctlr* ctlr;
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188 |
Ctlr* ramdac;
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Ctlr* clock;
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190 |
Ctlr* hwgc;
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Ctlr* vesa;
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Ctlr* link;
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int linear;
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Attr* attr;
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195 |
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void* private;
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} Vga;
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198 |
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199 |
/* 3dfx.c */
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extern Ctlr tdfx;
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201 |
extern Ctlr tdfxhwgc;
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202 |
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203 |
/* ark2000pv.c */
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204 |
extern Ctlr ark2000pv;
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extern Ctlr ark2000pvhwgc;
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206 |
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207 |
/* att20c49x.c */
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208 |
extern Ctlr att20c490;
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209 |
extern Ctlr att20c491;
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210 |
extern Ctlr att20c492;
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211 |
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212 |
/* att21c498.c */
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213 |
extern uchar attdaci(uchar);
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214 |
extern void attdaco(uchar, uchar);
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215 |
extern Ctlr att21c498;
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216 |
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217 |
/* bt485.c */
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218 |
extern uchar bt485i(uchar);
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219 |
extern void bt485o(uchar, uchar);
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220 |
extern Ctlr bt485;
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221 |
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222 |
/* ch9294.c */
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223 |
extern Ctlr ch9294;
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224 |
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225 |
/* clgd542x.c */
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226 |
extern void clgd54xxclock(Vga*, Ctlr*);
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227 |
extern Ctlr clgd542x;
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228 |
extern Ctlr clgd542xhwgc;
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229 |
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230 |
/* clgd546x.c */
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231 |
extern Ctlr clgd546x;
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232 |
extern Ctlr clgd546xhwgc;
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233 |
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234 |
/* ct65540.c */
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235 |
extern Ctlr ct65540;
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236 |
extern Ctlr ct65545;
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237 |
extern Ctlr ct65545hwgc;
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238 |
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239 |
/* cyber938x.c */
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240 |
extern Ctlr cyber938x;
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241 |
extern Ctlr cyber938xhwgc;
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242 |
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243 |
/* data.c */
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244 |
extern int cflag;
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245 |
extern int dflag;
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246 |
extern Ctlr *ctlrs[];
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247 |
extern ushort dacxreg[4];
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248 |
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249 |
/* db.c */
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250 |
extern char* dbattr(Attr*, char*);
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251 |
extern int dbctlr(char*, Vga*);
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252 |
extern Mode* dbmode(char*, char*, char*);
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253 |
extern void dbdumpmode(Mode*);
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254 |
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255 |
/* error.c */
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256 |
extern void error(char*, ...);
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257 |
extern void trace(char*, ...);
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258 |
extern int vflag, Vflag;
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259 |
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260 |
/* et4000.c */
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261 |
extern Ctlr et4000;
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262 |
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263 |
/* et4000hwgc.c */
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264 |
extern Ctlr et4000hwgc;
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265 |
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266 |
/* hiqvideo.c */
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267 |
extern Ctlr hiqvideo;
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268 |
extern Ctlr hiqvideohwgc;
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269 |
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270 |
/* i81x.c */
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271 |
extern Ctlr i81x;
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272 |
extern Ctlr i81xhwgc;
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273 |
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274 |
/* ibm8514.c */
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275 |
extern Ctlr ibm8514;
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276 |
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277 |
/* icd2061a.c */
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278 |
extern Ctlr icd2061a;
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279 |
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280 |
/* ics2494.c */
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281 |
extern Ctlr ics2494;
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282 |
extern Ctlr ics2494a;
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283 |
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284 |
/* ics534x.c */
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285 |
extern Ctlr ics534x;
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286 |
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287 |
/* io.c */
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288 |
extern uchar inportb(long);
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289 |
extern void outportb(long, uchar);
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290 |
extern ushort inportw(long);
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291 |
extern void outportw(long, ushort);
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292 |
extern ulong inportl(long);
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293 |
extern void outportl(long, ulong);
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294 |
extern char* vgactlr(char*, char*);
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295 |
extern void vgactlw(char*, char*);
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296 |
extern char* readbios(long, long);
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297 |
extern void dumpbios(long);
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298 |
extern void error(char*, ...);
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299 |
extern void* alloc(ulong);
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300 |
extern void printitem(char*, char*);
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301 |
extern void printreg(ulong);
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302 |
extern void printflag(ulong);
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303 |
extern void setpalette(int, int, int, int);
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304 |
extern int curprintindex;
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305 |
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306 |
/* mach32.c */
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307 |
extern Ctlr mach32;
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308 |
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309 |
/* mach64.c */
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310 |
extern Ctlr mach64;
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311 |
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312 |
/* mach64xx.c */
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313 |
extern Ctlr mach64xx;
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314 |
extern Ctlr mach64xxhwgc;
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315 |
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316 |
/* main.c */
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317 |
extern char* chanstr[];
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318 |
extern void resyncinit(Vga*, Ctlr*, ulong, ulong);
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319 |
extern void sequencer(Vga*, int);
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320 |
extern void main(int, char*[]);
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321 |
Biobuf stdout;
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322 |
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323 |
/* mga2164w.c */
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324 |
extern Ctlr mga2164w;
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325 |
extern Ctlr mga2164whwgc;
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326 |
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327 |
/* neomagic.c */
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328 |
extern Ctlr neomagic;
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329 |
extern Ctlr neomagichwgc;
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330 |
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331 |
/* nvidia.c */
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332 |
extern Ctlr nvidia;
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333 |
extern Ctlr nvidiahwgc;
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334 |
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335 |
/* radeon.c */
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336 |
extern Ctlr radeon;
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337 |
extern Ctlr radeonhwgc;
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338 |
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339 |
/* palette.c */
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340 |
extern Ctlr palette;
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341 |
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342 |
/* pci.c */
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343 |
typedef struct Pcidev Pcidev;
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344 |
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345 |
extern int pcicfgr8(Pcidev*, int);
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346 |
extern int pcicfgr16(Pcidev*, int);
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347 |
extern int pcicfgr32(Pcidev*, int);
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348 |
extern void pcicfgw8(Pcidev*, int, int);
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349 |
extern void pcicfgw16(Pcidev*, int, int);
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350 |
extern void pcicfgw32(Pcidev*, int, int);
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351 |
extern void pcihinv(Pcidev*);
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352 |
extern Pcidev* pcimatch(Pcidev*, int, int);
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353 |
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354 |
/* rgb524.c */
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355 |
extern Ctlr rgb524;
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356 |
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357 |
/* rgb524mn.c */
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358 |
extern uchar (*rgb524mnxi)(Vga*, int);
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359 |
extern void (*rgb524mnxo)(Vga*, int, uchar);
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360 |
extern Ctlr rgb524mn;
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361 |
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362 |
/* s3801.c */
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|
363 |
extern Ctlr s3801;
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364 |
extern Ctlr s3805;
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365 |
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366 |
/* s3928.c */
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367 |
extern Ctlr s3928;
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368 |
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369 |
/* s3clock.c */
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370 |
extern Ctlr s3clock;
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371 |
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372 |
/* s3generic.c */
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373 |
extern Ctlr s3generic;
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374 |
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375 |
/* s3hwgc.c */
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376 |
extern Ctlr bt485hwgc;
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377 |
extern Ctlr rgb524hwgc;
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378 |
extern Ctlr s3hwgc;
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379 |
extern Ctlr tvp3020hwgc;
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380 |
extern Ctlr tvp3026hwgc;
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381 |
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382 |
/* sc15025.c */
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383 |
extern Ctlr sc15025;
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384 |
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385 |
/* stg1702.c */
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386 |
extern Ctlr stg1702;
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387 |
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388 |
/* t2r4.c */
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389 |
extern Ctlr t2r4;
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390 |
extern Ctlr t2r4hwgc;
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391 |
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392 |
/* trio64.c */
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393 |
extern void trio64clock(Vga*, Ctlr*);
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394 |
extern Ctlr trio64;
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395 |
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396 |
/* tvp3020.c */
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397 |
extern uchar tvp3020i(uchar);
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398 |
extern uchar tvp3020xi(uchar);
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399 |
extern void tvp3020o(uchar, uchar);
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400 |
extern void tvp3020xo(uchar, uchar);
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401 |
extern Ctlr tvp3020;
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402 |
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403 |
/* tvp3025.c */
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404 |
extern Ctlr tvp3025;
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405 |
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406 |
/* tvp3025clock.c */
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407 |
extern Ctlr tvp3025clock;
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408 |
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409 |
/* tvp3026.c */
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410 |
extern uchar tvp3026xi(uchar);
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411 |
extern void tvp3026xo(uchar, uchar);
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412 |
extern Ctlr tvp3026;
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413 |
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414 |
/* tvp3026clock.c */
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415 |
extern Ctlr tvp3026clock;
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416 |
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417 |
/* vga.c */
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418 |
extern uchar vgai(long);
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419 |
extern uchar vgaxi(long, uchar);
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420 |
extern void vgao(long, uchar);
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421 |
extern void vgaxo(long, uchar, uchar);
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422 |
extern Ctlr generic;
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423 |
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424 |
/* vesa.c */
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425 |
extern Ctlr vesa;
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426 |
extern Ctlr softhwgc; /* has to go somewhere */
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427 |
extern int dbvesa(Vga*);
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428 |
extern Mode *dbvesamode(char*);
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429 |
extern void vesatextmode(void);
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430 |
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431 |
/* virge.c */
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432 |
extern Ctlr virge;
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433 |
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434 |
/* vision864.c */
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435 |
extern Ctlr vision864;
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436 |
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437 |
/* vision964.c */
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438 |
extern Ctlr vision964;
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439 |
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440 |
/* vision968.c */
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441 |
extern Ctlr vision968;
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442 |
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443 |
/* vmware.c */
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444 |
extern Ctlr vmware;
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445 |
extern Ctlr vmwarehwgc;
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446 |
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447 |
/* w30c516.c */
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448 |
extern Ctlr w30c516;
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449 |
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450 |
/* mga4xx.c */
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451 |
extern Ctlr mga4xx;
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452 |
extern Ctlr mga4xxhwgc;
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453 |
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454 |
#pragma varargck argpos error 1
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455 |
#pragma varargck argpos trace 1
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