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WebSVN – planix.SVN – Blame – /os/branches/feature_posix/sys/src/cmd/aux/vga/w30c516.c – Rev 2

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#include <u.h>
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#include <libc.h>
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#include <bio.h>
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#include "pci.h"
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#include "vga.h"
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/*
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 * IC Works W30C516 ZOOMDAC.
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 * DSP-based Multimedia RAMDAC.
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 */
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enum {
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	Cr0		= 0x00,		/* Control register 0 */
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	Mid		= 0x01,		/* Manufacturer's identification register */
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	Did		= 0x02,		/* Device identification register */
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	Cr1		= 0x03,		/* Control register 1 */
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	Reserve1	= 0x04,		/* Reserved (16-bit) */
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	Reserve2	= 0x06,		/* Reserved (16-bit) */
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	Reserve3	= 0x08,		/* Reserved (16-bit) */
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	Reserve4	= 0x0A,		/* Reserved (16-bit) */
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	IstartX		= 0x0C,		/* Image Start X (16-bit) */
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	IstartY		= 0x0E,		/* Image Start Y (16-bit) */
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	IendX		= 0x10,		/* Image End X (16-bit) */
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	IendY		= 0x12,		/* Image End Y (16-bit) */
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	RatioX		= 0x14,		/* Ratio X (16-bit) */
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	RatioY		= 0x16,		/* Ratio Y (16-bit) */
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	OffsetX		= 0x18,		/* Offset X (16-bit) */
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	OffsetY		= 0x1A,		/* Offset Y (16-bit) */
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	TestR		= 0x1C,		/* Red signature analysis register */
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	TestG		= 0x1D,		/* Green signature analysis register */
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	TestB		= 0x1E,		/* Blue signature analysis register */
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	Nir		= 0x1F,		/* number of indirect registers */
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};
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static void
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options(Vga*, Ctlr* ctlr)
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{
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	ctlr->flag |= Hpclk2x8|Foptions;
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}
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static void
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init(Vga* vga, Ctlr* ctlr)
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{
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	ulong grade, pclk;
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	char *p;
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	/*
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	 * Part comes in -170, -135 and -110MHz speed-grades.
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	 * In 8-bit mode the max. PCLK is 135MHz for the -170 part
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	 * and the speed-grade for the others. In 2x8-bit mode, the max.
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	 * PCLK is the speed-grade, using the 2x doubler.
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	 * Work out the part speed-grade from name. Name can have,
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	 * e.g. '-135' on the end  for 135MHz part.
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	 */
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	grade = 110000000;
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	if(p = strrchr(ctlr->name, '-'))
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		grade = strtoul(p+1, 0, 0) * 1000000;
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	if(grade == 170000000)
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		pclk = 135000000;
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	else
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		pclk = grade;
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	/*
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	 * If we don't already have a desired pclk,
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	 * take it from the mode.
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	 * Check it's within range.
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	 */
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	if(vga->f[0] == 0)
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		vga->f[0] = vga->mode->frequency;
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	/*
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	 * Determine whether to use 2x8-bit mode or not.
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	 * If yes and the clock has already been initialised,
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	 * initialise it again. There is no real frequency
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	 * restriction, it's really just a lower limit on what's
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	 * available in some clock generator chips.
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	 */
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	if(vga->ctlr && (vga->ctlr->flag & Hpclk2x8) && vga->mode->z == 8 && vga->f[0] >= 60000000){
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		vga->f[0] /= 2;
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		resyncinit(vga, ctlr, Upclk2x8, 0);
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	}
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	if(vga->f[0] > pclk)
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		error("%s: invalid pclk - %ld\n", ctlr->name, vga->f[0]);
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	ctlr->flag |= Finit;
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}
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static void
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load(Vga* vga, Ctlr* ctlr)
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{
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	uchar mode, x;
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	/*
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	 * Put the chip to sleep.
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	 */
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	attdaco(Cr0, 0x08);
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	mode = 0x00;
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	if(ctlr->flag & Upclk2x8)
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		mode = 0x20;
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	/*
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	 * Set the mode in the RAMDAC, setting 6/8-bit colour
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	 * as appropriate and waking the chip back up.
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	 */
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	if(vga->mode->z == 8 && 0)
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		mode |= 0x02;
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	x = attdaci(Cr1) & 0x80;
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	attdaco(Cr1, x);
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	attdaco(Cr0, mode);
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	ctlr->flag |= Fload;
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}
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static void
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dump(Vga*, Ctlr* ctlr)
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{
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	int i;
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	printitem(ctlr->name, "");
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	for(i = 0; i < Nir; i++)
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		printreg(attdaci(i));
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}
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Ctlr w30c516 = {
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	"w30c516",			/* name */
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	0,				/* snarf */
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	options,			/* options */
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	init,				/* init */
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	load,				/* load */
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	dump,				/* dump */
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};