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/*
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* armv6 reboot code
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*/
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#include "arm.s"
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/*
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* Turn off MMU, then copy the new kernel to its correct location
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* in physical memory. Then jump to the start of the kernel.
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*/
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/* main(PADDR(entry), PADDR(code), size); */
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TEXT main(SB), 1, $-4
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MOVW $setR12(SB), R12
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/* copy in arguments before stack gets unmapped */
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MOVW R0, R8 /* entry point */
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MOVW p2+4(FP), R9 /* source */
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MOVW n+8(FP), R10 /* byte count */
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/* SVC mode, interrupts disabled */
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
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MOVW R1, CPSR
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/* prepare to turn off mmu */
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BL cachesoff(SB)
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/* turn off mmu */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $CpCmmu, R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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/* set up a tiny stack for local vars and memmove args */
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MOVW R8, SP /* stack top just before kernel dest */
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SUB $20, SP /* allocate stack frame */
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/* copy the kernel to final destination */
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MOVW R8, 16(SP) /* save dest (entry point) */
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MOVW R8, R0 /* first arg is dest */
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MOVW R9, 8(SP) /* push src */
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MOVW R10, 12(SP) /* push size */
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BL memmove(SB)
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MOVW 16(SP), R8 /* restore entry point */
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/* jump to kernel physical entry point */
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B (R8)
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B 0(PC)
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/*
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* turn the caches off, double map PHYSDRAM & KZERO, invalidate TLBs, revert
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* to tiny addresses. upon return, it will be safe to turn off the mmu.
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* clobbers R0-R2, and returns with SP invalid.
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*/
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TEXT cachesoff(SB), 1, $-4
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/* write back and invalidate caches */
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BARRIERS
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEall
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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/* turn caches off */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $(CpCdcache|CpCicache|CpCpredict), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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/* invalidate stale TLBs before changing them */
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BARRIERS
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MOVW $KZERO, R0 /* some valid virtual address */
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* from here on, R0 is base of physical memory */
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MOVW $PHYSDRAM, R0
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/* redo double map of first MiB PHYSDRAM = KZERO */
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MOVW $(L1+L1X(PHYSDRAM)), R2 /* address of PHYSDRAM's PTE */
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MOVW $PTEDRAM, R1 /* PTE bits */
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ORR R0, R1 /* dram base */
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MOVW R1, (R2)
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/* invalidate stale TLBs again */
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BARRIERS
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* relocate SB and return address to PHYSDRAM addressing */
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MOVW $KSEGM, R1 /* clear segment bits */
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BIC R1, R12 /* adjust SB */
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ORR R0, R12
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BIC R1, R14 /* adjust return address */
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ORR R0, R14
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RET
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