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mikrotik rb450g routerboard
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3 |
atheros ar7161 cpu: mips 24Kc v3.5 rev 0: 30 dec 2005,
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big-endian, 32-bit only, 8- or 9-stage pipeline; 8kb cache
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option, but no l2 support, no relocatable reset exception
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vector, no UserLocal register, no wait with interrupts
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disabled, no errata fixes.
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no fpu
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9 |
256mb dram
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mmu 16 tlbs
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l1 i-cache 4 ways, 512 sets, 32 bytes per line = 64K
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l1 d-cache 4 ways, 256 sets, 32 bytes per line = 32k
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config1: 0x9ee3519e
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config2: 0x80000000 (no l2 cache)
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config3: 0x20 (VInt: vectored interrupts available)
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config7: 0 (wait instruction not interruptible)
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cause: 0x50008018 (original interrupt behaviour)
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intctl: 0 (original interrupt behaviour)
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srsctl, srsmap are 0
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perf ctl 0: 0x80000000
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perf ctl 1: 0x0
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ll/sc target memory must be cached.
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1 uart 8250 (actually 16550ish)
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2 ethers arge[01] ar71xx, 2nd has 4 ports & a bridge
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pci bus(es)
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no video
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no disk but has flash, alas
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addresses
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devices; access by KSEG1|addr
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0x10000000 pci memory space
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0x18020000 uart 16550 in apb space
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0x19000000 ether arge1, phy0-3
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0x1a000000 ether arge0, phy4
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0x1b000000 ehci
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0x1c000000 ochi
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0x1f000000 spi
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0x80060000 virtual start addr (linux)
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0xbfc00000 prom
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irqs
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2 pci
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3 ehci
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4 arge1 ar71xx @ 0x19:: + ar8316 switch
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5 arge0 ar71xx @ 0x1a::
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6 uart
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7 clock
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apb intrs
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1 error
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2 gpio
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3 uart
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4 watchdog
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5 hwpmc
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6 ohci
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7 dma
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for previous mips assembler code, see
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/1998/0101/sys/src/boot/carrera
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/1998/0101/sys/src/brazil/carrera
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/2000/0615/sys/src/9/carrera
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/n/fornaxdump/1997/1201/sys/src/brazil/magnum
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for ether, see
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/o/bsd/free/sys/mips/atheros/if_arge.c
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/o/bsd/free/sys/mips/atheros/if_argevar.h
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/o/bsd/free/sys/mips/atheros/ar71xxreg.h
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/o/bsd/free/sys/dev/etherswitch/*
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/o/openwrt/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx
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