| 2 |
- |
1 |
/*
|
|
|
2 |
* Memory and machine-specific definitions. Used in C and assembler.
|
|
|
3 |
*/
|
|
|
4 |
#define KiB 1024u /* Kibi 0x0000000000000400 */
|
|
|
5 |
#define MiB 1048576u /* Mebi 0x0000000000100000 */
|
|
|
6 |
#define GiB 1073741824u /* Gibi 000000000040000000 */
|
|
|
7 |
|
|
|
8 |
/*
|
|
|
9 |
* Not sure where these macros should go.
|
|
|
10 |
* This probably isn't right but will do for now.
|
|
|
11 |
* The macro names are problematic too.
|
|
|
12 |
*/
|
|
|
13 |
/*
|
|
|
14 |
* In BITN(o), 'o' is the bit offset in the register.
|
|
|
15 |
* For multi-bit fields use F(v, o, w) where 'v' is the value
|
|
|
16 |
* of the bit-field of width 'w' with LSb at bit offset 'o'.
|
|
|
17 |
*/
|
|
|
18 |
#define BITN(o) (1<<(o))
|
|
|
19 |
#define F(v, o, w) (((v) & ((1<<(w))-1))<<(o))
|
|
|
20 |
|
|
|
21 |
/*
|
|
|
22 |
* Sizes
|
|
|
23 |
*/
|
|
|
24 |
#define BY2PG (4*KiB) /* bytes per page */
|
|
|
25 |
#define PGSHIFT 12 /* log(BY2PG) */
|
|
|
26 |
|
|
|
27 |
/* max # of cpus system can run. tegra2 cpu ids are two bits wide. */
|
|
|
28 |
#define MAXMACH 4
|
|
|
29 |
#define MACHSIZE BY2PG
|
|
|
30 |
#define L1SIZE (4 * BY2PG)
|
|
|
31 |
|
|
|
32 |
#define KSTKSIZE (16*KiB) /* was 8K */
|
|
|
33 |
#define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */
|
|
|
34 |
|
|
|
35 |
/*
|
|
|
36 |
* Magic registers
|
|
|
37 |
*/
|
|
|
38 |
|
|
|
39 |
#define USER 9 /* R9 is up-> */
|
|
|
40 |
#define MACH 10 /* R10 is m-> */
|
|
|
41 |
|
|
|
42 |
/*
|
|
|
43 |
* Address spaces.
|
|
|
44 |
* KTZERO is used by kprof and dumpstack (if any).
|
|
|
45 |
*
|
|
|
46 |
* KZERO (0xc0000000) is mapped to physical 0 (start of dram).
|
|
|
47 |
* u-boot claims to occupy the first 4 MB of dram, but we're willing to
|
|
|
48 |
* step on it once we're loaded.
|
|
|
49 |
*
|
|
|
50 |
* L2 PTEs are stored in 4K before cpu0's Mach (8K to 12K above KZERO).
|
|
|
51 |
* cpu0's Mach struct is at L1 - MACHSIZE(4K) to L1 (12K to 16K above KZERO).
|
|
|
52 |
* L1 PTEs are stored from L1 to L1+32K (16K to 48K above KZERO).
|
|
|
53 |
* plan9.ini is loaded at CONFADDR (4MB).
|
|
|
54 |
* KTZERO may be anywhere after that.
|
|
|
55 |
*/
|
|
|
56 |
#define KSEG0 0xC0000000 /* kernel segment */
|
|
|
57 |
/* mask to check segment; good for 1GB dram */
|
|
|
58 |
#define KSEGM 0xC0000000
|
|
|
59 |
#define KZERO KSEG0 /* kernel address space */
|
|
|
60 |
#define L1 (KZERO+16*KiB) /* cpu0 l1 page table; 16KiB aligned */
|
|
|
61 |
#define CONFADDR (KZERO+0x400000) /* unparsed plan9.ini */
|
|
|
62 |
#define CACHECONF (CONFADDR+48*KiB)
|
|
|
63 |
/* KTZERO must match loadaddr in mkfile */
|
|
|
64 |
#define KTZERO (KZERO+0x410000) /* kernel text start */
|
|
|
65 |
|
|
|
66 |
#define L2pages (2*MiB) /* high memory reserved for l2 page tables */
|
|
|
67 |
#define RESRVDHIMEM (64*KiB + MiB + L2pages) /* avoid HVECTOR, l2 pages */
|
|
|
68 |
/* we assume that we have 1 GB of ram, which is true for all trimslices. */
|
|
|
69 |
#define DRAMSIZE GiB
|
|
|
70 |
|
|
|
71 |
#define UZERO 0 /* user segment */
|
|
|
72 |
#define UTZERO (UZERO+BY2PG) /* user text start */
|
|
|
73 |
#define UTROUND(t) ROUNDUP((t), BY2PG)
|
|
|
74 |
/*
|
|
|
75 |
* moved USTKTOP down to 1GB to keep MMIO space out of user space.
|
|
|
76 |
* moved it down another MB to utterly avoid KADDR(stack_base) mapping
|
|
|
77 |
* to high exception vectors. see confinit().
|
|
|
78 |
*/
|
|
|
79 |
#define USTKTOP (0x40000000 - 64*KiB - MiB) /* user segment end +1 */
|
|
|
80 |
#define USTKSIZE (8*1024*1024) /* user stack size */
|
|
|
81 |
#define TSTKTOP (USTKTOP-USTKSIZE) /* sysexec temporary stack */
|
|
|
82 |
#define TSTKSIZ 256
|
|
|
83 |
|
|
|
84 |
/* address at which to copy and execute rebootcode */
|
|
|
85 |
#define REBOOTADDR KADDR(0x100)
|
|
|
86 |
|
|
|
87 |
/*
|
|
|
88 |
* Legacy...
|
|
|
89 |
*/
|
|
|
90 |
#define BLOCKALIGN CACHELINESZ /* only used in allocb.c */
|
|
|
91 |
#define KSTACK KSTKSIZE
|
|
|
92 |
|
|
|
93 |
/*
|
|
|
94 |
* Sizes
|
|
|
95 |
*/
|
|
|
96 |
#define BI2BY 8 /* bits per byte */
|
|
|
97 |
#define BY2SE 4
|
|
|
98 |
#define BY2WD 4
|
|
|
99 |
#define BY2V 8 /* only used in xalloc.c */
|
|
|
100 |
|
|
|
101 |
#define CACHELINESZ 32 /* bytes per cache line */
|
|
|
102 |
#define PTEMAPMEM (1024*1024)
|
|
|
103 |
#define PTEPERTAB (PTEMAPMEM/BY2PG)
|
|
|
104 |
#define SEGMAPSIZE 1984 /* magic 16*124 */
|
|
|
105 |
#define SSEGMAPSIZE 16 /* magic */
|
|
|
106 |
#define PPN(x) ((x)&~(BY2PG-1)) /* pure page number? */
|
|
|
107 |
|
|
|
108 |
/*
|
|
|
109 |
* With a little work these move to port.
|
|
|
110 |
*/
|
|
|
111 |
#define PTEVALID (1<<0)
|
|
|
112 |
#define PTERONLY 0
|
|
|
113 |
#define PTEWRITE (1<<1)
|
|
|
114 |
#define PTEUNCACHED (1<<2)
|
|
|
115 |
#define PTEKERNEL (1<<3)
|
|
|
116 |
|
|
|
117 |
/*
|
|
|
118 |
* Physical machine information from here on.
|
|
|
119 |
*/
|
|
|
120 |
|
|
|
121 |
#define PHYSDRAM 0
|
|
|
122 |
|
|
|
123 |
#define PHYSIO 0x50000000 /* cpu */
|
|
|
124 |
#define VIRTIO PHYSIO
|
|
|
125 |
#define PHYSL2BAG 0x50043000 /* l2 cache bag-on-the-side */
|
|
|
126 |
#define PHYSEVP 0x6000f100 /* undocumented `exception vector' */
|
|
|
127 |
#define PHYSCONS 0x70006000 /* uart console */
|
|
|
128 |
#define PHYSIOEND 0xc0000000 /* end of ahb mem & pcie */
|
|
|
129 |
|
|
|
130 |
#define PHYSAHB 0xc0000000 /* ahb bus */
|
|
|
131 |
#define VIRTAHB 0xb0000000
|
|
|
132 |
#define P2VAHB(pa) ((pa) - PHYSAHB + VIRTAHB)
|
|
|
133 |
|
|
|
134 |
#define PHYSNOR 0xd0000000
|
|
|
135 |
#define VIRTNOR 0x40000000
|