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WebSVN – planix.SVN – Blame – /os/branches/feature_tlsv12/sys/src/libmp/power/mpvecdigmulsub.s – Rev 2

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#define	BDNZ	BC	16,0,
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#define	BDNE	BC	0,2,
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#define	BLT	BC	0xC,0,
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/*
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 *	mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
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 *
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 *	p -= b*m
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 *
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 *	each step looks like:
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 *		hi,lo = m*b[i]
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 *		lo += oldhi + carry
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 *		hi += carry
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 *		p[i] += lo
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 *		oldhi = hi
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 *
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 *	the registers are:
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 *		b = R3
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 *		n = R4
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 *		m = R5
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 *		p = R6
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 *		i = R7
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 *		hi = R8		- constrained by hardware
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 *		lo = R9		- constrained by hardware
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 *		oldhi = R10
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 *		tmp = R11
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 *		borrow = R12
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 *
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 */
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TEXT	mpvecdigmulsub(SB),$0
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	MOVW	n+4(FP),R10
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	MOVW	R10,CTR
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	MOVW	m+8(FP),R5
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	MOVW	p+12(FP),R6
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	SUB	$4, R3		/* pre decrement for MOVWU's */
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	SUBC	$4, R6		/* pre decrement for MOVWU's and set carry */
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	MOVW	XER,R12
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	MOVW	R0, R10
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_mulsubloop:
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	MOVWU	4(R3),R9	/* lo = b[i] */
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	MOVW	4(R6),R11	/* tmp = p[i] */
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	MULHWU	R9,R5,R8	/* hi = (b[i] * m)>>32 */
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	MULLW	R9,R5,R9	/* lo = b[i] * m */
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	ADDC	R10,R9		/* lo += oldhi */
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	ADDE	R0,R8		/* hi += carry */
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	MOVW	R12,XER
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	SUBE	R9,R11		/* tmp -= lo */
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	MOVW	XER,R12
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	MOVWU	R11,4(R6)	/* p[i] = tmp */
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	MOVW	R8,R10		/* oldhi = hi */
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	BDNZ	_mulsubloop
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	MOVW	4(R6),R11	/* tmp = p[i] */
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	MOVW	R12,XER
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	SUBE	R10,R11		/* tmp -= lo */
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	MOVWU	R11,4(R6)	/* p[i] = tmp */
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	/* return -1 if the result was negative, +1 otherwise */
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	SUBECC	R0,R0,R3
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	BLT	_mulsub2
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	MOVW	$1,R3
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_mulsub2:
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	RETURN