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1 |
enum {
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2 |
IrqCLOCK = 0,
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3 |
IrqKBD = 1,
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4 |
IrqUART1 = 3,
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5 |
IrqUART0 = 4,
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6 |
IrqPCMCIA = 5,
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7 |
IrqFLOPPY = 6,
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8 |
IrqLPT = 7,
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9 |
IrqIRQ7 = 7,
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10 |
IrqAUX = 12, /* PS/2 port */
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11 |
IrqIRQ13 = 13, /* coprocessor on 386 */
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12 |
IrqATA0 = 14,
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13 |
IrqATA1 = 15,
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14 |
MaxIrqPIC = 15,
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15 |
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16 |
VectorPIC = 32,
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17 |
MaxVectorPIC = VectorPIC+MaxIrqPIC,
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18 |
};
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19 |
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20 |
typedef struct Vctl {
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21 |
Vctl* next; /* handlers on this vector */
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22 |
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char name[KNAMELEN]; /* of driver */
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24 |
int isintr; /* interrupt or fault/trap */
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25 |
int irq;
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int tbdf;
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int (*isr)(int); /* get isr bit for this irq */
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28 |
int (*eoi)(int); /* eoi */
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29 |
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30 |
void (*f)(Ureg*, void*); /* handler to call */
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void* a; /* argument to call it with */
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32 |
} Vctl;
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33 |
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enum {
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BusCBUS = 0, /* Corollary CBUS */
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36 |
BusCBUSII, /* Corollary CBUS II */
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37 |
BusEISA, /* Extended ISA */
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38 |
BusFUTURE, /* IEEE Futurebus */
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39 |
BusINTERN, /* Internal bus */
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40 |
BusISA, /* Industry Standard Architecture */
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41 |
BusMBI, /* Multibus I */
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42 |
BusMBII, /* Multibus II */
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43 |
BusMCA, /* Micro Channel Architecture */
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44 |
BusMPI, /* MPI */
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45 |
BusMPSA, /* MPSA */
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46 |
BusNUBUS, /* Apple Macintosh NuBus */
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47 |
BusPCI, /* Peripheral Component Interconnect */
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48 |
BusPCMCIA, /* PC Memory Card International Association */
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49 |
BusTC, /* DEC TurboChannel */
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50 |
BusVL, /* VESA Local bus */
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51 |
BusVME, /* VMEbus */
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52 |
BusXPRESS, /* Express System Bus */
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53 |
};
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54 |
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55 |
#define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
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56 |
#define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
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57 |
#define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
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58 |
#define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
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59 |
#define BUSTYPE(tbdf) ((tbdf)>>24)
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60 |
#define BUSDF(tbdf) ((tbdf)&0x000FF00)
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61 |
#define BUSBDF(tbdf) ((tbdf)&0x0FFFF00)
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62 |
#define BUSUNKNOWN (-1)
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63 |
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64 |
enum {
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MaxEISA = 16,
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66 |
EISAconfig = 0xC80,
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};
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68 |
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69 |
/*
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70 |
* PCI support code.
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71 |
*/
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72 |
enum { /* type 0 and type 1 pre-defined header */
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PciVID = 0x00, /* vendor ID */
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74 |
PciDID = 0x02, /* device ID */
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75 |
PciPCR = 0x04, /* command */
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76 |
PciPSR = 0x06, /* status */
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77 |
PciRID = 0x08, /* revision ID */
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78 |
PciCCRp = 0x09, /* programming interface class code */
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79 |
PciCCRu = 0x0A, /* sub-class code */
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80 |
PciCCRb = 0x0B, /* base class code */
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81 |
PciCLS = 0x0C, /* cache line size */
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82 |
PciLTR = 0x0D, /* latency timer */
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83 |
PciHDT = 0x0E, /* header type */
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84 |
PciBST = 0x0F, /* BIST */
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85 |
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86 |
PciBAR0 = 0x10, /* base address */
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87 |
PciBAR1 = 0x14,
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88 |
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89 |
PciINTL = 0x3C, /* interrupt line */
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90 |
PciINTP = 0x3D, /* interrupt pin */
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91 |
};
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92 |
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enum { /* type 0 pre-defined header */
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PciCIS = 0x28, /* cardbus CIS pointer */
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95 |
PciSVID = 0x2C, /* subsystem vendor ID */
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96 |
PciSID = 0x2E, /* cardbus CIS pointer */
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97 |
PciEBAR0 = 0x30, /* expansion ROM base address */
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98 |
PciMGNT = 0x3E, /* burst period length */
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99 |
PciMLT = 0x3F, /* maximum latency between bursts */
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100 |
};
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101 |
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102 |
enum { /* type 1 pre-defined header */
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103 |
PciPBN = 0x18, /* primary bus number */
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104 |
PciSBN = 0x19, /* secondary bus number */
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105 |
PciUBN = 0x1A, /* subordinate bus number */
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106 |
PciSLTR = 0x1B, /* secondary latency timer */
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107 |
PciIBR = 0x1C, /* I/O base */
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108 |
PciILR = 0x1D, /* I/O limit */
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109 |
PciSPSR = 0x1E, /* secondary status */
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110 |
PciMBR = 0x20, /* memory base */
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111 |
PciMLR = 0x22, /* memory limit */
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112 |
PciPMBR = 0x24, /* prefetchable memory base */
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113 |
PciPMLR = 0x26, /* prefetchable memory limit */
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114 |
PciPUBR = 0x28, /* prefetchable base upper 32 bits */
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115 |
PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
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116 |
PciIUBR = 0x30, /* I/O base upper 16 bits */
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117 |
PciIULR = 0x32, /* I/O limit upper 16 bits */
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118 |
PciEBAR1 = 0x28, /* expansion ROM base address */
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119 |
PciBCR = 0x3E, /* bridge control register */
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120 |
};
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121 |
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122 |
enum { /* type 2 pre-defined header */
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123 |
PciCBExCA = 0x10,
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124 |
PciCBSPSR = 0x16,
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125 |
PciCBPBN = 0x18, /* primary bus number */
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126 |
PciCBSBN = 0x19, /* secondary bus number */
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127 |
PciCBUBN = 0x1A, /* subordinate bus number */
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128 |
PciCBSLTR = 0x1B, /* secondary latency timer */
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129 |
PciCBMBR0 = 0x1C,
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130 |
PciCBMLR0 = 0x20,
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131 |
PciCBMBR1 = 0x24,
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132 |
PciCBMLR1 = 0x28,
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133 |
PciCBIBR0 = 0x2C, /* I/O base */
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134 |
PciCBILR0 = 0x30, /* I/O limit */
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135 |
PciCBIBR1 = 0x34, /* I/O base */
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136 |
PciCBILR1 = 0x38, /* I/O limit */
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137 |
PciCBSVID = 0x40, /* subsystem vendor ID */
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138 |
PciCBSID = 0x42, /* subsystem ID */
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139 |
PciCBLMBAR = 0x44, /* legacy mode base address */
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140 |
};
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141 |
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142 |
typedef struct Pcisiz Pcisiz;
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143 |
struct Pcisiz
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144 |
{
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145 |
Pcidev* dev;
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146 |
int siz;
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147 |
int bar;
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148 |
};
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149 |
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150 |
typedef struct Pcidev Pcidev;
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151 |
typedef struct Pcidev {
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152 |
int tbdf; /* type+bus+device+function */
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153 |
ushort vid; /* vendor ID */
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154 |
ushort did; /* device ID */
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155 |
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156 |
uchar rid;
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157 |
uchar ccrp;
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158 |
uchar ccru;
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159 |
uchar ccrb;
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160 |
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161 |
struct {
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162 |
ulong bar; /* base address */
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163 |
int size;
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164 |
} mem[6];
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165 |
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166 |
uchar intl; /* interrupt line */
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167 |
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168 |
Pcidev* list;
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169 |
Pcidev* link; /* next device on this bno */
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170 |
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171 |
Pcidev* bridge; /* down a bus */
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172 |
struct {
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173 |
ulong bar;
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174 |
int size;
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175 |
} ioa, mema;
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176 |
ulong pcr;
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177 |
};
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178 |
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179 |
#define PCIWINDOW 0x80000000
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180 |
#define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
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