| 2 |
- |
1 |
/*
|
|
|
2 |
* Memory and machine-specific definitions. Used in C and assembler.
|
|
|
3 |
*/
|
|
|
4 |
#define KiB 1024u /* Kibi 0x0000000000000400 */
|
|
|
5 |
#define MiB 1048576u /* Mebi 0x0000000000100000 */
|
|
|
6 |
#define GiB 1073741824u /* Gibi 000000000040000000 */
|
|
|
7 |
|
|
|
8 |
/*
|
|
|
9 |
* Sizes
|
|
|
10 |
*/
|
|
|
11 |
|
|
|
12 |
#define BI2BY 8 /* bits per byte */
|
|
|
13 |
#define BI2WD 32 /* bits per word */
|
|
|
14 |
#define BY2WD 4 /* bytes per word */
|
|
|
15 |
#define BY2V 8 /* bytes per vlong */
|
|
|
16 |
#define BY2PG 4096 /* bytes per page */
|
|
|
17 |
#define WD2PG (BY2PG/BY2WD) /* words per page */
|
|
|
18 |
#define PGSHIFT 12 /* log(BY2PG) */
|
|
|
19 |
#define CACHELINELOG 4
|
|
|
20 |
#define CACHELINESZ (1<<CACHELINELOG)
|
|
|
21 |
#define BLOCKALIGN CACHELINESZ
|
|
|
22 |
|
|
|
23 |
#define MHz 1000000
|
|
|
24 |
|
|
|
25 |
#define BY2PTE 8 /* bytes per pte entry */
|
|
|
26 |
#define BY2PTEG 64 /* bytes per pte group */
|
|
|
27 |
|
|
|
28 |
#define MAXMACH 1 /* max # cpus system can run */
|
|
|
29 |
#define MACHSIZE BY2PG
|
|
|
30 |
#define KSTACK 4096 /* Size of kernel stack */
|
|
|
31 |
|
|
|
32 |
/*
|
|
|
33 |
* Time
|
|
|
34 |
*/
|
|
|
35 |
#define HZ 100 /* clock frequency */
|
|
|
36 |
#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
|
|
|
37 |
|
|
|
38 |
/*
|
|
|
39 |
* Standard PPC Special Purpose Registers (OEA and VEA)
|
|
|
40 |
*/
|
|
|
41 |
#define DSISR 18
|
|
|
42 |
#define DAR 19 /* Data Address Register */
|
|
|
43 |
#define DEC 22 /* Decrementer */
|
|
|
44 |
#define SDR1 25
|
|
|
45 |
#define SRR0 26 /* Saved Registers (exception) */
|
|
|
46 |
#define SRR1 27
|
|
|
47 |
#define SPRG0 272 /* Supervisor Private Registers */
|
|
|
48 |
#define SPRG1 273
|
|
|
49 |
#define SPRG2 274
|
|
|
50 |
#define SPRG3 275
|
|
|
51 |
#define ASR 280 /* Address Space Register */
|
|
|
52 |
#define EAR 282 /* External Access Register (optional) */
|
|
|
53 |
#define TBRU 269 /* Time base Upper/Lower (Reading) */
|
|
|
54 |
#define TBRL 268
|
|
|
55 |
#define TBWU 284 /* Time base Upper/Lower (Writing) */
|
|
|
56 |
#define TBWL 285
|
|
|
57 |
#define PVR 287 /* Processor Version */
|
|
|
58 |
#define IABR 1010 /* Instruction Address Breakpoint Register (optional) */
|
|
|
59 |
#define DABR 1013 /* Data Address Breakpoint Register (optional) */
|
|
|
60 |
#define FPECR 1022 /* Floating-Point Exception Cause Register (optional) */
|
|
|
61 |
#define PIR 1023 /* Processor Identification Register (optional) */
|
|
|
62 |
|
|
|
63 |
#define IBATU(i) (528+2*(i)) /* Instruction BAT register (upper) */
|
|
|
64 |
#define IBATL(i) (529+2*(i)) /* Instruction BAT register (lower) */
|
|
|
65 |
#define DBATU(i) (536+2*(i)) /* Data BAT register (upper) */
|
|
|
66 |
#define DBATL(i) (537+2*(i)) /* Data BAT register (lower) */
|
|
|
67 |
|
|
|
68 |
/*
|
|
|
69 |
* PPC604e-specific Special Purpose Registers (OEA)
|
|
|
70 |
*/
|
|
|
71 |
#define HID0 1008 /* Hardware Implementation Dependant Register 0 */
|
|
|
72 |
#define HID1 1009 /* Hardware Implementation Dependant Register 1 */
|
|
|
73 |
#define PMC1 953 /* Performance Monitor Counter 1 */
|
|
|
74 |
#define PMC2 954 /* Performance Monitor Counter 2 */
|
|
|
75 |
#define PMC3 957 /* Performance Monitor Counter 3 */
|
|
|
76 |
#define PMC4 958 /* Performance Monitor Counter 4 */
|
|
|
77 |
#define MMCR0 952 /* Monitor Control Register 0 */
|
|
|
78 |
#define MMCR1 956 /* Monitor Control Register 0 */
|
|
|
79 |
#define SIA 955 /* Sampled Instruction Address */
|
|
|
80 |
#define SDA 959 /* Sampled Data Address */
|
|
|
81 |
|
|
|
82 |
#define BIT(i) (1<<(31-(i))) /* Silly backwards register bit numbering scheme */
|
|
|
83 |
|
|
|
84 |
/*
|
|
|
85 |
* Bit encodings for Machine State Register (MSR)
|
|
|
86 |
*/
|
|
|
87 |
#define MSR_POW BIT(13) /* Enable Power Management */
|
|
|
88 |
#define MSR_ILE BIT(15) /* Interrupt Little-Endian enable */
|
|
|
89 |
#define MSR_EE BIT(16) /* External Interrupt enable */
|
|
|
90 |
#define MSR_PR BIT(17) /* Supervisor/User privelege */
|
|
|
91 |
#define MSR_FP BIT(18) /* Floating Point enable */
|
|
|
92 |
#define MSR_ME BIT(19) /* Machine Check enable */
|
|
|
93 |
#define MSR_FE0 BIT(20) /* Floating Exception mode 0 */
|
|
|
94 |
#define MSR_SE BIT(21) /* Single Step (optional) */
|
|
|
95 |
#define MSR_BE BIT(22) /* Branch Trace (optional) */
|
|
|
96 |
#define MSR_FE1 BIT(23) /* Floating Exception mode 1 */
|
|
|
97 |
#define MSR_IP BIT(25) /* Exception prefix 0x000/0xFFF */
|
|
|
98 |
#define MSR_IR BIT(26) /* Instruction MMU enable */
|
|
|
99 |
#define MSR_DR BIT(27) /* Data MMU enable */
|
|
|
100 |
#define MSR_PM BIT(29) /* Performance Monitor marked mode (604e specific) */
|
|
|
101 |
#define MSR_RI BIT(30) /* Recoverable Exception */
|
|
|
102 |
#define MSR_LE BIT(31) /* Little-Endian enable */
|
|
|
103 |
|
|
|
104 |
/*
|
|
|
105 |
* Exception codes (trap vectors)
|
|
|
106 |
*/
|
|
|
107 |
#define CRESET 0x01
|
|
|
108 |
#define CMCHECK 0x02
|
|
|
109 |
#define CDSI 0x03
|
|
|
110 |
#define CISI 0x04
|
|
|
111 |
#define CEI 0x05
|
|
|
112 |
#define CALIGN 0x06
|
|
|
113 |
#define CPROG 0x07
|
|
|
114 |
#define CFPU 0x08
|
|
|
115 |
#define CDEC 0x09
|
|
|
116 |
#define CSYSCALL 0x0C
|
|
|
117 |
#define CTRACE 0x0D /* optional */
|
|
|
118 |
#define CFPA 0x0E /* optional */
|
|
|
119 |
|
|
|
120 |
/* PPC604e-specific: */
|
|
|
121 |
#define CPERF 0x0F /* performance monitoring */
|
|
|
122 |
#define CIBREAK 0x13
|
|
|
123 |
#define CSMI 0x14
|
|
|
124 |
|
|
|
125 |
/*
|
|
|
126 |
* Magic registers
|
|
|
127 |
*/
|
|
|
128 |
|
|
|
129 |
#define MACH 30 /* R30 is m-> */
|
|
|
130 |
#define USER 29 /* R29 is up-> */
|
|
|
131 |
|
|
|
132 |
|
|
|
133 |
/*
|
|
|
134 |
* virtual MMU
|
|
|
135 |
*/
|
|
|
136 |
#define PTEMAPMEM (1024*1024)
|
|
|
137 |
#define PTEPERTAB (PTEMAPMEM/BY2PG)
|
|
|
138 |
#define SEGMAPSIZE 1984
|
|
|
139 |
#define SSEGMAPSIZE 16
|
|
|
140 |
#define PPN(x) ((x)&~(BY2PG-1))
|
|
|
141 |
|
|
|
142 |
/*
|
|
|
143 |
* First pte word
|
|
|
144 |
*/
|
|
|
145 |
#define PTE0(v, vsid, h, va) (((v)<<31)|((vsid)<<7)|((h)<<6)|(((va)>>22)&0x3f))
|
|
|
146 |
|
|
|
147 |
/*
|
|
|
148 |
* Second pte word; WIMG & PP(RW/RO) common to page table and BATs
|
|
|
149 |
*/
|
|
|
150 |
#define PTE1_W BIT(25)
|
|
|
151 |
#define PTE1_I BIT(26)
|
|
|
152 |
#define PTE1_M BIT(27)
|
|
|
153 |
#define PTE1_G BIT(28)
|
|
|
154 |
|
|
|
155 |
#define PTE1_RW BIT(30)
|
|
|
156 |
#define PTE1_RO BIT(31)
|
|
|
157 |
|
|
|
158 |
/*
|
|
|
159 |
* PTE bits for fault.c. These belong to the second PTE word. Validity is
|
|
|
160 |
* implied for putmmu(), and we always set PTE0_V. PTEVALID is used
|
|
|
161 |
* here to set cache policy bits on a global basis.
|
|
|
162 |
*/
|
|
|
163 |
#define PTEVALID 0
|
|
|
164 |
#define PTEWRITE PTE1_RW
|
|
|
165 |
#define PTERONLY PTE1_RO
|
|
|
166 |
#define PTEUNCACHED PTE1_I
|
|
|
167 |
|
|
|
168 |
/*
|
|
|
169 |
* Address spaces
|
|
|
170 |
*/
|
|
|
171 |
|
|
|
172 |
#define UZERO 0 /* base of user address space */
|
|
|
173 |
#define UTZERO (UZERO+BY2PG) /* first address in user text */
|
|
|
174 |
#define UTROUND(t) ROUNDUP((t), 0x100000)
|
|
|
175 |
#define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
|
|
|
176 |
#define TSTKTOP KZERO /* top of temporary stack */
|
|
|
177 |
#define TSTKSIZ 100
|
|
|
178 |
#define KZERO 0x80000000 /* base of kernel address space */
|
|
|
179 |
#define KTZERO (KZERO+0x4000) /* first address in kernel text */
|
|
|
180 |
#define USTKSIZE (4*1024*1024) /* size of user stack */
|
|
|
181 |
#define UREGSIZE ((8+32)*4)
|
|
|
182 |
|
|
|
183 |
#define PCIMEM0 0xf0000000
|
|
|
184 |
#define PCISIZE0 0x0e000000
|
|
|
185 |
#define PCIMEM1 0xc0000000
|
|
|
186 |
#define PCISIZE1 0x30000000
|
|
|
187 |
#define IOMEM 0xfe000000
|
|
|
188 |
#define IOSIZE 0x00800000
|
|
|
189 |
#define FALCON 0xfef80000
|
|
|
190 |
#define RAVEN 0xfeff0000
|
|
|
191 |
#define FLASHA 0xff000000
|
|
|
192 |
#define FLASHB 0xff800000
|
|
|
193 |
#define FLASHAorB 0xfff00000
|
|
|
194 |
|
|
|
195 |
#define isphys(x) (((ulong)x&KZERO)!=0)
|
|
|
196 |
|
|
|
197 |
#define getpgcolor(a) 0
|