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/*
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* cortex arm arch v7 cache flushing and invalidation
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* shared by l.s and rebootcode.s
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*/
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TEXT cacheiinv(SB), $-4 /* I invalidate */
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall /* ok on cortex */
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ISB
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RET
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/*
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* set/way operators, passed a suitable set/way value in R0.
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*/
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TEXT cachedwb_sw(SB), $-4
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEsi
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RET
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TEXT cachedwbinv_sw(SB), $-4
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEsi
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RET
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TEXT cachedinv_sw(SB), $-4
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvd), CpCACHEsi
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RET
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/* set cache size select */
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TEXT setcachelvl(SB), $-4
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MCR CpSC, CpIDcssel, R0, C(CpID), C(CpIDidct), 0
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ISB
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RET
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/* return cache sizes */
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TEXT getwayssets(SB), $-4
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MRC CpSC, CpIDcsize, R0, C(CpID), C(CpIDidct), 0
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RET
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/*
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* l1 cache operations.
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* l1 and l2 ops are intended to be called from C, thus need save no
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* caller's regs, only those we need to preserve across calls.
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*/
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TEXT cachedwb(SB), $-4
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MOVW.W R14, -8(R13)
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MOVW $cachedwb_sw(SB), R0
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MOVW $1, R8
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BL wholecache(SB)
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MOVW.P 8(R13), R15
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TEXT cachedwbinv(SB), $-4
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MOVW.W R14, -8(R13)
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MOVW $cachedwbinv_sw(SB), R0
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MOVW $1, R8
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BL wholecache(SB)
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MOVW.P 8(R13), R15
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TEXT cachedinv(SB), $-4
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MOVW.W R14, -8(R13)
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MOVW $cachedinv_sw(SB), R0
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MOVW $1, R8
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BL wholecache(SB)
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MOVW.P 8(R13), R15
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TEXT cacheuwbinv(SB), $-4
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MOVM.DB.W [R14], (R13) /* save lr on stack */
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MOVW CPSR, R1
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CPSID /* splhi */
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MOVM.DB.W [R1], (R13) /* save R1 on stack */
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BL cachedwbinv(SB)
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BL cacheiinv(SB)
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MOVM.IA.W (R13), [R1] /* restore R1 (saved CPSR) */
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MOVW R1, CPSR
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MOVM.IA.W (R13), [R14] /* restore lr */
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RET
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/*
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* l2 cache operations
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*/
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TEXT l2cacheuwb(SB), $-4
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MOVW.W R14, -8(R13)
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MOVW $cachedwb_sw(SB), R0
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MOVW $2, R8
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BL wholecache(SB)
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MOVW.P 8(R13), R15
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TEXT l2cacheuwbinv(SB), $-4
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MOVW.W R14, -8(R13)
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MOVW CPSR, R1
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CPSID /* splhi */
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MOVM.DB.W [R1], (R13) /* save R1 on stack */
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MOVW $cachedwbinv_sw(SB), R0
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MOVW $2, R8
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BL wholecache(SB)
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BL l2cacheuinv(SB)
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MOVM.IA.W (R13), [R1] /* restore R1 (saved CPSR) */
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MOVW R1, CPSR
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MOVW.P 8(R13), R15
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TEXT l2cacheuinv(SB), $-4
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MOVW.W R14, -8(R13)
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MOVW $cachedinv_sw(SB), R0
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MOVW $2, R8
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BL wholecache(SB)
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MOVW.P 8(R13), R15
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/*
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* these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
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* the Cortex-A8 L2 cache (A=3, L=6).
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* A = log2(# of ways), L = log2(bytes per cache line).
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* see armv7 arch ref p. 1403.
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*/
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#define L1WAYSH 30
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#define L1SETSH 6
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#define L2WAYSH 29
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#define L2SETSH 6
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/*
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* callers are assumed to be the above l1 and l2 ops.
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* R0 is the function to call in the innermost loop.
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* R8 is the cache level (one-origin: 1 or 2).
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*
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* initial translation by 5c, then massaged by hand.
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*/
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TEXT wholecache+0(SB), $-4
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MOVW R0, R1 /* save argument for inner loop in R1 */
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SUB $1, R8 /* convert cache level to zero origin */
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/* we may not have the MMU on yet, so map R1 to PC's space */
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BIC $KSEGM, R1 /* strip segment from address */
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MOVW PC, R2 /* get PC's segment ... */
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AND $KSEGM, R2
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CMP $0, R2 /* PC segment should be non-zero on omap */
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BEQ buggery
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ORR R2, R1 /* combine them */
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/* drain write buffers */
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BARRIERS
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
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ISB
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MOVW CPSR, R2
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MOVM.DB.W [R2,R14], (SP) /* save regs on stack */
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CPSID /* splhi to make entire op atomic */
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/* get cache sizes */
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SLL $1, R8, R0 /* R0 = (cache - 1) << 1 */
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MCR CpSC, CpIDcssel, R0, C(CpID), C(CpIDidct), 0 /* set cache size select */
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ISB
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MRC CpSC, CpIDcsize, R0, C(CpID), C(CpIDidct), 0 /* get cache sizes */
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/* compute # of ways and sets for this cache level */
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SRA $3, R0, R5 /* R5 (ways) = R0 >> 3 */
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AND $1023, R5 /* R5 = (R0 >> 3) & MASK(10) */
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ADD $1, R5 /* R5 (ways) = ((R0 >> 3) & MASK(10)) + 1 */
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SRA $13, R0, R2 /* R2 = R0 >> 13 */
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AND $32767, R2 /* R2 = (R0 >> 13) & MASK(15) */
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ADD $1, R2 /* R2 (sets) = ((R0 >> 13) & MASK(15)) + 1 */
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/* precompute set/way shifts for inner loop */
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CMP $0, R8 /* cache == 1? */
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MOVW.EQ $L1WAYSH, R3 /* yes */
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MOVW.EQ $L1SETSH, R4
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MOVW.NE $L2WAYSH, R3 /* no */
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MOVW.NE $L2SETSH, R4
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/* iterate over ways */
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MOVW $0, R7 /* R7: way */
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outer:
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/* iterate over sets */
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MOVW $0, R6 /* R6: set */
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inner:
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/* compute set/way register contents */
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SLL R3, R7, R0 /* R0 = way << R3 (L?WAYSH) */
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ORR R8<<1, R0 /* R0 = way << L?WAYSH | (cache - 1) << 1 */
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ORR R6<<R4, R0 /* R0 = way<<L?WAYSH | (cache-1)<<1 |set<<R4 */
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BL (R1) /* call set/way operation with R0 */
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ADD $1, R6 /* set++ */
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CMP R2, R6 /* set >= sets? */
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BLT inner /* no, do next set */
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ADD $1, R7 /* way++ */
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CMP R5, R7 /* way >= ways? */
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BLT outer /* no, do next way */
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MOVM.IA.W (SP), [R2,R14] /* restore regs */
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MOVW R2, CPSR /* splx */
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/* drain write buffers */
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
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ISB
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RET
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buggery:
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PUTC('?')
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MOVW PC, R0
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// B pczeroseg(SB)
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RET
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