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beagleboard rev c3:
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cortex-a8 cpu: arm v7-a arch. rev 3, 500MHz, dual-issue
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OMAP3530-GP rev 2, CPU-OPP2 L3-165MHz
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OMAP3 Beagle board + LPDDR/NAND
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DRAM: 256 MB
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NAND: 256 MiB
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Board revision C
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Serial #784200230000000004013f790401d018
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igepv2 board:
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cortex-a8 cpu: arm v7-a arch. rev 3, 720MHz, dual-issue
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OMAP3530-GP ES3.1, CPU-OPP2 L3-165MHz
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IGEP v2.x rev. B + LPDDR/ONENAND
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DRAM: 512 MB
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Muxed OneNAND(DDP) 512MB 1.8V 16-bit (0x58)
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OneNAND version = 0x0031
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Chip support all block unlock
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Chip has 2 plane
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Scanning device for bad blocks
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Bad eraseblock 3134 at 0x187c0000
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Bad eraseblock 3135 at 0x187e0000
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OneNAND: 512 MB
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omap3530 SoC
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CORE_CLK runs at 26MHz
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see spruf98d from ti.com (/public/doc/ti/omap35x.ref.spruf98d.pdf)
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separate i & d tlbs, each 32 entries
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can invalidate i, d or both tlbs by { all, mva, or asid match }
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i & d L1 caches, 16K each, 4 ways, 64 sets, 64-byte lines
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i is VIPT, d is PIPT
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no `test and clean D & U all' operations
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no prefetching, no cache maintenance
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can invalidate i, d or both cache but not D & U all
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can invalidate entire i-cache only
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can clean or invalidate by set and way data/unified cache
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unified L2 PIPT cache, 256K, 8 ways, 512 sets, 64-byte lines
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no hardware cache coherence
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l3 interconnect firewalls are all off at boot time, except for a bit of
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secure ram
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sram at 0x40200000 size 1MB
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l4 interconnect firewalls seem to be sane at boot time
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___
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The state of the Beagleboard/IGEPv2 (TI OMAP35 SoC, Cortex-A8) port.
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Plan 9 runs on the IGEPv2 and Gumstix Overo boards.
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On the Beagleboard, Plan 9 is not yet usable but it gets as far as
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trying to access the USB ethernet (since the Beagleboard has no
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built-in ethernet and must use USB ethernet).
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IGEP & Gumstix Ethernet
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The smsc9221 ethernet consumes a lot of system time. The design
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decision to use fifos rather than buffer rings and to not incorporate
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dma into the ethernet controller is probably responsible. With only a
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single core, running the 9221 consumes a lot of the available CPU
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time. It's probably worth trying to use the system dma controller again.
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USB
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The ohci and ehci controllers are seen, but no devices yet.
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There are four USB errata that need to be looked into for the igepv2
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(silicon 3.1) at least. From the omap3530 errata (rev e):
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- 3.1.1.130 only one usb dma channel (rx or tx) can be active
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at one time: use interrupt mode instead
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- 3.1.1.144 otg soft reset doesn't work right
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- 3.1.1.183 ohci and ehci controllers cannot work concurrently
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- §3.1.3 usb limitations: all ports must be configured to identical speeds
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(high vs full/low)
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Flash
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access to nand flash would be handy for nvram and paqfs file systems.
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In the flash, x-loader occupies up to 0x20000, then u-boot from
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0x80000 to 0x1e0000, and there's a linux kernel after that (if you
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care). The beagle's flash chip is a micron pop 2Gb nand
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mt29f2g16abdhc-et (physical marking jw256), and the igep's is a
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samsung onenand.
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VFPv3 Floating Point
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The Cortex-A8 has VFPv3 floating point, which uses different opcodes
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than 5c/5l currently generate. New 5c or 5l is in the works.
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Video
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The display subsystem for omap3 (dss) is divided into 3 parts, called lcd,
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video and dsi (ignoring the various accelerators). The system only
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supports the lcd via dvi interface so far because it's the only one we
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have been able to test. 1280x1024x16 is the default resolution, this
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might be changed. Writing to /dev/dssctl (e.g., echo 1024x768x16
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>/dev/dssctl) changes the resolution. Currently the system does not
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use the rfbi since it seems like an unnecessary optimisation at this
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point. Per Odlund wrote the first draft of the video driver for a
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Google Summer of Code project.
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Stray Interrupts
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IRQs 56 and 57 are I2C. 83, 86 and 94 are MMC.
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___
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The code is fairly heavy-handed with the use of barrier instructions
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(BARRIERS in assembler, coherence in C), partly in reaction to bad
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experience doing Power PC ports, but also just as precautions against
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modern processors, which may feel free to execute instructions out of
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order or some time later, store to memory out of order or some time
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later, otherwise break the model of traditional sequential processors,
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or any combination of the above.
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___
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There are a few rough edges:
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- the clock.c scheduling rate (HZ) is quite approximate. The OMAP
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timers are complex, but one could eventually do better (or just let
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timesync compensate).
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- User processes are limited to 512MB virtual (mainly by the IGEPv2 Ethernet
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being at 0x2c000000), which isn't a problem since Beagleboards only
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have 256MB of dram and IGEPv2s have 512MB, and we don't want to swap.
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- might use ucalloc.c to allocate uncached scratch space for generated code
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in coproc.c.
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131 |
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- the C implementation of cache primitives failed with mmu off; still true?
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133 |
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- unlock, setup: protect module register target APE (PM_RT) per spruf98c §1.6.7
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- setup mpp (multi-purpose pins)?
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___
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memory map (mostly from omap35x ref)
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hex addr size what
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----
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20000000 16MB virtual address of flash registers, buffers
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2c000000 ? smc 9221 ethernet
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38000000 16MB 256MB (beagle) or 512MB (igep) nand flash mapped here
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40000000 112K boot rom, top of user space
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40200000 64K sram
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48000000 16MB L4 core
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48002000 8K system control (scm)
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48004000 16K clock manager
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48040000 8K L4-core config
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48050000 4K graphics
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48062000 4K usb tll
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48064000 1K usb uhh_config
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48064400 1K ohci
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48064800 1K ehci
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4806a000 8K 8250 uart0
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4806c000 8K 8250 uart1
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48086000 4K gptimer10
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48088000 4K gptimer11
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4809c000 8K mmc/sd goo
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480ab000 8K hs usb otg
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480ad000 8K mmc/sd goo
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480b4000 8K mmc/sd goo
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480c7000 device intr controller
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48200000 2K intr ctlr (intc)
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48300000 256K L4-wakeup
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48304000 4K gptimer12
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48318000 8K gptimer1
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49000000 1MB L4 peripherals
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49020000 8K 8250 uart2 (with exposed connector for console)
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49032000 4K gptimer2
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49034000 4K gptimer3
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⋯
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49040000 4K gptimer9
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49050000 8K gpio2
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⋯
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49058000 8K gpio6
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50000000 64K graphics accelerator
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68000000 1K L3 config (rt)
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68004000 1K L3 hs usb host
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68004400 1K L3 hs usb otg
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68005400 1K L3 graphics
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68006800 1K L4-core config
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68010000 L3 protection mechanism
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6e000000 ? gpmc
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80000000 256MB dram on beagle
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512MB dram on igep
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c0000000 1GB kernel virtual space, mapped to 80000000
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apparently the vector address (0 or 0xffff0000) is virtual,
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so we're expected to map it to ram.
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