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enum {
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BusCBUS = 0, /* Corollary CBUS */
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BusCBUSII, /* Corollary CBUS II */
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BusEISA, /* Extended ISA */
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BusFUTURE, /* IEEE Futurebus */
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BusINTERN, /* Internal bus */
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BusISA, /* Industry Standard Architecture */
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BusMBI, /* Multibus I */
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BusMBII, /* Multibus II */
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BusMCA, /* Micro Channel Architecture */
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BusMPI, /* MPI */
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BusMPSA, /* MPSA */
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BusNUBUS, /* Apple Macintosh NuBus */
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BusPCI, /* Peripheral Component Interconnect */
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BusPCMCIA, /* PC Memory Card International Association */
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BusTC, /* DEC TurboChannel */
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BusVL, /* VESA Local bus */
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BusVME, /* VMEbus */
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BusXPRESS, /* Express System Bus */
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};
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#define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
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#define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
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#define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
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#define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
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#define BUSTYPE(tbdf) ((tbdf)>>24)
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#define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
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#define BUSUNKNOWN (-1)
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/*
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* PCI support code.
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*/
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enum { /* type 0 and type 1 pre-defined header */
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PciVID = 0x00, /* vendor ID */
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PciDID = 0x02, /* device ID */
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PciPCR = 0x04, /* command */
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PciPSR = 0x06, /* status */
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PciRID = 0x08, /* revision ID */
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PciCCRp = 0x09, /* programming interface class code */
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PciCCRu = 0x0A, /* sub-class code */
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PciCCRb = 0x0B, /* base class code */
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PciCLS = 0x0C, /* cache line size */
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PciLTR = 0x0D, /* latency timer */
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PciHDT = 0x0E, /* header type */
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PciBST = 0x0F, /* BIST */
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PciBAR0 = 0x10, /* base address */
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PciBAR1 = 0x14,
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PciINTL = 0x3C, /* interrupt line */
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PciINTP = 0x3D, /* interrupt pin */
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};
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enum { /* type 0 pre-defined header */
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PciBAR2 = 0x18,
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PciBAR3 = 0x1C,
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PciBAR4 = 0x20,
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PciBAR5 = 0x24,
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PciCIS = 0x28, /* cardbus CIS pointer */
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PciSVID = 0x2C, /* subsystem vendor ID */
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PciSID = 0x2E, /* cardbus CIS pointer */
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PciEBAR0 = 0x30, /* expansion ROM base address */
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PciMGNT = 0x3E, /* burst period length */
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PciMLT = 0x3F, /* maximum latency between bursts */
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};
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enum { /* type 1 pre-defined header */
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PciPBN = 0x18, /* primary bus number */
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PciSBN = 0x19, /* secondary bus number */
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PciUBN = 0x1A, /* subordinate bus number */
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PciSLTR = 0x1B, /* secondary latency timer */
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PciIBR = 0x1C, /* I/O base */
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PciILR = 0x1D, /* I/O limit */
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PciSPSR = 0x1E, /* secondary status */
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PciMBR = 0x20, /* memory base */
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PciMLR = 0x22, /* memory limit */
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PciPMBR = 0x24, /* prefetchable memory base */
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PciPMLR = 0x26, /* prefetchable memory limit */
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PciPUBR = 0x28, /* prefetchable base upper 32 bits */
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PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
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PciIUBR = 0x30, /* I/O base upper 16 bits */
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PciIULR = 0x32, /* I/O limit upper 16 bits */
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PciEBAR1 = 0x28, /* expansion ROM base address */
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PciBCR = 0x3E, /* bridge control register */
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};
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typedef struct Pcidev Pcidev;
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typedef struct Pcidev {
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int tbdf; /* type+bus+device+function */
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ushort vid; /* vendor ID */
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ushort did; /* device ID */
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uchar rid; /* revision ID */
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struct {
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ulong bar; /* base address */
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int size;
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} mem[6];
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uchar intl; /* interrupt line */
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ushort ccru;
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101 |
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102 |
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Pcidev* list;
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Pcidev* bridge; /* down a bus */
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Pcidev* link; /* next device on this bno */
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};
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