WebSVN – planix.SVN – Blame – /os/branches/planix-v0/sys/src/9/pc/ether82563.c

Rev	Author	Line No.	Line
2	-	1	`/*`
		2	`* Intel Gigabit Ethernet PCI-Express Controllers.`
		3	`* 8256[36], 8257[1-79]`
		4	`* Pretty basic, does not use many of the chip smarts.`
		5	`* The interrupt mitigation tuning for each chip variant`
		6	`* is probably different. The reset/initialisation`
		7	`* sequence needs straightened out. Doubt the PHY code`
		8	`* for the 82575eb is right.`
		9	`*/`
		10	`#include "u.h"`
		11	`#include "../port/lib.h"`
		12	`#include "mem.h"`
		13	`#include "dat.h"`
		14	`#include "fns.h"`
		15	`#include "io.h"`
		16	`#include "../port/error.h"`
		17	`#include "../port/netif.h"`
		18
		19	`#include "etherif.h"`
		20
		21	`/*`
		22	`* these are in the order they appear in the manual, not numeric order.`
		23	`* It was too hard to find them in the book. Ref 21489, rev 2.6`
		24	`*/`
		25
		26	`enum {`
		27	`/* General */`
		28
		29	`Ctrl = 0x0000, /* Device Control */`
		30	`Status = 0x0008, /* Device Status */`
		31	`Eec = 0x0010, /* EEPROM/Flash Control/Data */`
		32	`Eerd = 0x0014, /* EEPROM Read */`
		33	`Ctrlext = 0x0018, /* Extended Device Control */`
		34	`Fla = 0x001c, /* Flash Access */`
		35	`Mdic = 0x0020, /* MDI Control */`
		36	`Seresctl = 0x0024, /* Serdes ana */`
		37	`Fcal = 0x0028, /* Flow Control Address Low */`
		38	`Fcah = 0x002C, /* Flow Control Address High */`
		39	`Fct = 0x0030, /* Flow Control Type */`
		40	`Kumctrlsta = 0x0034, /* MAC-PHY Interface */`
		41	`Vet = 0x0038, /* VLAN EtherType */`
		42	`Fcttv = 0x0170, /* Flow Control Transmit Timer Value */`
		43	`Txcw = 0x0178, /* Transmit Configuration Word */`
		44	`Rxcw = 0x0180, /* Receive Configuration Word */`
		45	`Ledctl = 0x0E00, /* LED control */`
		46	`Pba = 0x1000, /* Packet Buffer Allocation */`
		47	`Pbs = 0x1008, /* Packet Buffer Size */`
		48
		49	`/* Interrupt */`
		50
		51	`Icr = 0x00C0, /* Interrupt Cause Read */`
		52	`Itr = 0x00c4, /* Interrupt Throttling Rate */`
		53	`Ics = 0x00C8, /* Interrupt Cause Set */`
		54	`Ims = 0x00D0, /* Interrupt Mask Set/Read */`
		55	`Imc = 0x00D8, /* Interrupt mask Clear */`
		56	`Iam = 0x00E0, /* Interrupt acknowledge Auto Mask */`
		57
		58	`/* Receive */`
		59
		60	`Rctl = 0x0100, /* Control */`
		61	`Ert = 0x2008, /* Early Receive Threshold (573[EVL], 579 only) */`
		62	`Fcrtl = 0x2160, /* Flow Control RX Threshold Low */`
		63	`Fcrth = 0x2168, /* Flow Control Rx Threshold High */`
		64	`Psrctl = 0x2170, /* Packet Split Receive Control */`
		65	`Rdbal = 0x2800, /* Rdesc Base Address Low Queue 0 */`
		66	`Rdbah = 0x2804, /* Rdesc Base Address High Queue 0 */`
		67	`Rdlen = 0x2808, /* Descriptor Length Queue 0 */`
		68	`Rdh = 0x2810, /* Descriptor Head Queue 0 */`
		69	`Rdt = 0x2818, /* Descriptor Tail Queue 0 */`
		70	`Rdtr = 0x2820, /* Descriptor Timer Ring */`
		71	`Rxdctl = 0x2828, /* Descriptor Control */`
		72	`Radv = 0x282C, /* Interrupt Absolute Delay Timer */`
		73	`Rdbal1 = 0x2900, /* Rdesc Base Address Low Queue 1 */`
		74	`Rdbah1 = 0x2804, /* Rdesc Base Address High Queue 1 */`
		75	`Rdlen1 = 0x2908, /* Descriptor Length Queue 1 */`
		76	`Rdh1 = 0x2910, /* Descriptor Head Queue 1 */`
		77	`Rdt1 = 0x2918, /* Descriptor Tail Queue 1 */`
		78	`Rxdctl1 = 0x2928, /* Descriptor Control Queue 1 */`
		79	`Rsrpd = 0x2c00, /* Small Packet Detect */`
		80	`Raid = 0x2c08, /* ACK interrupt delay */`
		81	`Cpuvec = 0x2c10, /* CPU Vector */`
		82	`Rxcsum = 0x5000, /* Checksum Control */`
		83	`Rfctl = 0x5008, /* Filter Control */`
		84	`Mta = 0x5200, /* Multicast Table Array */`
		85	`Ral = 0x5400, /* Receive Address Low */`
		86	`Rah = 0x5404, /* Receive Address High */`
		87	`Vfta = 0x5600, /* VLAN Filter Table Array */`
		88	`Mrqc = 0x5818, /* Multiple Receive Queues Command */`
		89	`Rssim = 0x5864, /* RSS Interrupt Mask */`
		90	`Rssir = 0x5868, /* RSS Interrupt Request */`
		91	`Reta = 0x5c00, /* Redirection Table */`
		92	`Rssrk = 0x5c80, /* RSS Random Key */`
		93
		94	`/* Transmit */`
		95
		96	`Tctl = 0x0400, /* Transmit Control */`
		97	`Tipg = 0x0410, /* Transmit IPG */`
		98	`Tkabgtxd = 0x3004, /* glci afe band gap transmit ref data, or something */`
		99	`Tdbal = 0x3800, /* Tdesc Base Address Low */`
		100	`Tdbah = 0x3804, /* Tdesc Base Address High */`
		101	`Tdlen = 0x3808, /* Descriptor Length */`
		102	`Tdh = 0x3810, /* Descriptor Head */`
		103	`Tdt = 0x3818, /* Descriptor Tail */`
		104	`Tidv = 0x3820, /* Interrupt Delay Value */`
		105	`Txdctl = 0x3828, /* Descriptor Control */`
		106	`Tadv = 0x382C, /* Interrupt Absolute Delay Timer */`
		107	`Tarc0 = 0x3840, /* Arbitration Counter Queue 0 */`
		108	`Tdbal1 = 0x3900, /* Descriptor Base Low Queue 1 */`
		109	`Tdbah1 = 0x3904, /* Descriptor Base High Queue 1 */`
		110	`Tdlen1 = 0x3908, /* Descriptor Length Queue 1 */`
		111	`Tdh1 = 0x3910, /* Descriptor Head Queue 1 */`
		112	`Tdt1 = 0x3918, /* Descriptor Tail Queue 1 */`
		113	`Txdctl1 = 0x3928, /* Descriptor Control 1 */`
		114	`Tarc1 = 0x3940, /* Arbitration Counter Queue 1 */`
		115
		116	`/* Statistics */`
		117
		118	`Statistics = 0x4000, /* Start of Statistics Area */`
		119	`Gorcl = 0x88/4, /* Good Octets Received Count */`
		120	`Gotcl = 0x90/4, /* Good Octets Transmitted Count */`
		121	`Torl = 0xC0/4, /* Total Octets Received */`
		122	`Totl = 0xC8/4, /* Total Octets Transmitted */`
		123	`Nstatistics = 0x124/4,`
		124	`};`
		125
		126	`enum { /* Ctrl */`
		127	`GIOmd = 1<<2, /* BIO master disable */`
		128	`Lrst = 1<<3, /* link reset */`
		129	`Slu = 1<<6, /* Set Link Up */`
		130	`SspeedMASK = 3<<8, /* Speed Selection */`
		131	`SspeedSHIFT = 8,`
		132	`Sspeed10 = 0x00000000, /* 10Mb/s */`
		133	`Sspeed100 = 0x00000100, /* 100Mb/s */`
		134	`Sspeed1000 = 0x00000200, /* 1000Mb/s */`
		135	`Frcspd = 1<<11, /* Force Speed */`
		136	`Frcdplx = 1<<12, /* Force Duplex */`
		137	`SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */`
		138	`SwdpinsloSHIFT = 18,`
		139	`SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */`
		140	`SwdpioloSHIFT = 22,`
		141	`Devrst = 1<<26, /* Device Reset */`
		142	`Rfce = 1<<27, /* Receive Flow Control Enable */`
		143	`Tfce = 1<<28, /* Transmit Flow Control Enable */`
		144	`Vme = 1<<30, /* VLAN Mode Enable */`
		145	`Phyrst = 1<<31, /* Phy Reset */`
		146	`};`
		147
		148	`enum { /* Status */`
		149	`Lu = 1<<1, /* Link Up */`
		150	`Lanid = 3<<2, /* mask for Lan ID. */`
		151	`Txoff = 1<<4, /* Transmission Paused */`
		152	`Tbimode = 1<<5, /* TBI Mode Indication */`
		153	`Phyra = 1<<10, /* PHY Reset Asserted */`
		154	`GIOme = 1<<19, /* GIO Master Enable Status */`
		155	`};`
		156
		157	`enum { /* Eerd */`
		158	`EEstart = 1<<0, /* Start Read */`
		159	`EEdone = 1<<1, /* Read done */`
		160	`};`
		161
		162	`enum { /* Ctrlext */`
		163	`Asdchk = 1<<12, /* ASD Check */`
		164	`Eerst = 1<<13, /* EEPROM Reset */`
		165	`Spdbyps = 1<<15, /* Speed Select Bypass */`
		166	`};`
		167
		168	`enum { /* EEPROM content offsets */`
		169	`Ea = 0x00, /* Ethernet Address */`
		170	`Cf = 0x03, /* Compatibility Field */`
		171	`Icw1 = 0x0A, /* Initialization Control Word 1 */`
		172	`Sid = 0x0B, /* Subsystem ID */`
		173	`Svid = 0x0C, /* Subsystem Vendor ID */`
		174	`Did = 0x0D, /* Device ID */`
		175	`Vid = 0x0E, /* Vendor ID */`
		176	`Icw2 = 0x0F, /* Initialization Control Word 2 */`
		177	`};`
		178
		179	`enum { /* Mdic */`
		180	`MDIdMASK = 0x0000FFFF, /* Data */`
		181	`MDIdSHIFT = 0,`
		182	`MDIrMASK = 0x001F0000, /* PHY Register Address */`
		183	`MDIrSHIFT = 16,`
		184	`MDIpMASK = 0x03E00000, /* PHY Address */`
		185	`MDIpSHIFT = 21,`
		186	`MDIwop = 0x04000000, /* Write Operation */`
		187	`MDIrop = 0x08000000, /* Read Operation */`
		188	`MDIready = 0x10000000, /* End of Transaction */`
		189	`MDIie = 0x20000000, /* Interrupt Enable */`
		190	`MDIe = 0x40000000, /* Error */`
		191	`};`
		192
		193	`enum { /* phy interface registers */`
		194	`Phyctl = 0, /* phy ctl */`
		195	`Physsr = 17, /* phy secondary status */`
		196	`Phyier = 18, /* 82573 phy interrupt enable */`
		197	`Phyisr = 19, /* 82563 phy interrupt status */`
		198	`Phylhr = 19, /* 8257[12] link health */`
		199
		200	`Rtlink = 1<<10, /* realtime link status */`
		201	`Phyan = 1<<11, /* phy has auto-negotiated */`
		202
		203	`/* Phyctl bits */`
		204	`Ran = 1<<9, /* restart auto-negotiation */`
		205	`Ean = 1<<12, /* enable auto-negotiation */`
		206
		207	`/* 82573 Phyier bits */`
		208	`Lscie = 1<<10, /* link status changed ie */`
		209	`Ancie = 1<<11, /* auto-negotiation complete ie */`
		210	`Spdie = 1<<14, /* speed changed ie */`
		211	`Panie = 1<<15, /* phy auto-negotiation error ie */`
		212
		213	`/* Phylhr/Phyisr bits */`
		214	`Anf = 1<<6, /* lhr: auto-negotiation fault */`
		215	`Ane = 1<<15, /* isr: auto-negotiation error */`
		216	`};`
		217
		218	`enum { /* Icr, Ics, Ims, Imc */`
		219	`Txdw = 0x00000001, /* Transmit Descriptor Written Back */`
		220	`Txqe = 0x00000002, /* Transmit Queue Empty */`
		221	`Lsc = 0x00000004, /* Link Status Change */`
		222	`Rxseq = 0x00000008, /* Receive Sequence Error */`
		223	`Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */`
		224	`Rxo = 0x00000040, /* Receiver Overrun */`
		225	`Rxt0 = 0x00000080, /* Receiver Timer Interrupt */`
		226	`Mdac = 0x00000200, /* MDIO Access Completed */`
		227	`Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */`
		228	`Gpi0 = 0x00000800, /* General Purpose Interrupts */`
		229	`Gpi1 = 0x00001000,`
		230	`Gpi2 = 0x00002000,`
		231	`Gpi3 = 0x00004000,`
		232	`Ack = 0x00020000, /* Receive ACK frame */`
		233	`};`
		234
		235	`enum { /* Txcw */`
		236	`TxcwFd = 0x00000020, /* Full Duplex */`
		237	`TxcwHd = 0x00000040, /* Half Duplex */`
		238	`TxcwPauseMASK = 0x00000180, /* Pause */`
		239	`TxcwPauseSHIFT = 7,`
		240	`TxcwPs = 1<<TxcwPauseSHIFT, /* Pause Supported */`
		241	`TxcwAs = 2<<TxcwPauseSHIFT, /* Asymmetric FC desired */`
		242	`TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */`
		243	`TxcwRfiSHIFT = 12,`
		244	`TxcwNpr = 0x00008000, /* Next Page Request */`
		245	`TxcwConfig = 0x40000000, /* Transmit Config Control */`
		246	`TxcwAne = 0x80000000, /* Auto-Negotiation Enable */`
		247	`};`
		248
		249	`enum { /* Rctl */`
		250	`Rrst = 0x00000001, /* Receiver Software Reset */`
		251	`Ren = 0x00000002, /* Receiver Enable */`
		252	`Sbp = 0x00000004, /* Store Bad Packets */`
		253	`Upe = 0x00000008, /* Unicast Promiscuous Enable */`
		254	`Mpe = 0x00000010, /* Multicast Promiscuous Enable */`
		255	`Lpe = 0x00000020, /* Long Packet Reception Enable */`
		256	`LbmMASK = 0x000000C0, /* Loopback Mode */`
		257	`LbmOFF = 0x00000000, /* No Loopback */`
		258	`LbmTBI = 0x00000040, /* TBI Loopback */`
		259	`LbmMII = 0x00000080, /* GMII/MII Loopback */`
		260	`LbmXCVR = 0x000000C0, /* Transceiver Loopback */`
		261	`RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */`
		262	`RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */`
		263	`RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */`
		264	`RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */`
		265	`MoMASK = 0x00003000, /* Multicast Offset */`
		266	`Bam = 0x00008000, /* Broadcast Accept Mode */`
		267	`BsizeMASK = 0x00030000, /* Receive Buffer Size */`
		268	`Bsize16384 = 0x00010000, /* Bsex = 1 */`
		269	`Bsize8192 = 0x00020000, /* Bsex = 1 */`
		270	`Bsize2048 = 0x00000000,`
		271	`Bsize1024 = 0x00010000,`
		272	`Bsize512 = 0x00020000,`
		273	`Bsize256 = 0x00030000,`
		274	`BsizeFlex = 0x08000000, /* Flexible Bsize in 1KB increments */`
		275	`Vfe = 0x00040000, /* VLAN Filter Enable */`
		276	`Cfien = 0x00080000, /* Canonical Form Indicator Enable */`
		277	`Cfi = 0x00100000, /* Canonical Form Indicator value */`
		278	`Dpf = 0x00400000, /* Discard Pause Frames */`
		279	`Pmcf = 0x00800000, /* Pass MAC Control Frames */`
		280	`Bsex = 0x02000000, /* Buffer Size Extension */`
		281	`Secrc = 0x04000000, /* Strip CRC from incoming packet */`
		282	`};`
		283
		284	`enum { /* Tctl */`
		285	`Trst = 0x00000001, /* Transmitter Software Reset */`
		286	`Ten = 0x00000002, /* Transmit Enable */`
		287	`Psp = 0x00000008, /* Pad Short Packets */`
		288	`Mulr = 0x10000000, /* Allow multiple concurrent requests */`
		289	`CtMASK = 0x00000FF0, /* Collision Threshold */`
		290	`CtSHIFT = 4,`
		291	`ColdMASK = 0x003FF000, /* Collision Distance */`
		292	`ColdSHIFT = 12,`
		293	`Swxoff = 0x00400000, /* Sofware XOFF Transmission */`
		294	`Pbe = 0x00800000, /* Packet Burst Enable */`
		295	`Rtlc = 0x01000000, /* Re-transmit on Late Collision */`
		296	`Nrtu = 0x02000000, /* No Re-transmit on Underrrun */`
		297	`};`
		298
		299	`enum { /* [RT]xdctl */`
		300	`PthreshMASK = 0x0000003F, /* Prefetch Threshold */`
		301	`PthreshSHIFT = 0,`
		302	`HthreshMASK = 0x00003F00, /* Host Threshold */`
		303	`HthreshSHIFT = 8,`
		304	`WthreshMASK = 0x003F0000, /* Writeback Threshold */`
		305	`WthreshSHIFT = 16,`
		306	`Gran = 0x01000000, /* Granularity */`
		307	`Qenable = 0x02000000, /* Queue Enable (82575) */`
		308	`};`
		309
		310	`enum { /* Rxcsum */`
		311	`PcssMASK = 0x00FF, /* Packet Checksum Start */`
		312	`PcssSHIFT = 0,`
		313	`Ipofl = 0x0100, /* IP Checksum Off-load Enable */`
		314	`Tuofl = 0x0200, /* TCP/UDP Checksum Off-load Enable */`
		315	`};`
		316
		317	`enum { /* Receive Delay Timer Ring */`
		318	`DelayMASK = 0xFFFF, /* delay timer in 1.024nS increments */`
		319	`DelaySHIFT = 0,`
		320	`Fpd = 0x80000000, /* Flush partial Descriptor Block */`
		321	`};`
		322
		323	`typedef struct Ctlr Ctlr;`
		324	`typedef struct Rd Rd;`
		325	`typedef struct Td Td;`
		326
		327	`struct Rd { /* Receive Descriptor */`
		328	`u32int addr[2];`
		329	`u16int length;`
		330	`u16int checksum;`
		331	`u8int status;`
		332	`u8int errors;`
		333	`u16int special;`
		334	`};`
		335
		336	`enum { /* Rd status */`
		337	`Rdd = 0x01, /* Descriptor Done */`
		338	`Reop = 0x02, /* End of Packet */`
		339	`Ixsm = 0x04, /* Ignore Checksum Indication */`
		340	`Vp = 0x08, /* Packet is 802.1Q (matched VET) */`
		341	`Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */`
		342	`Ipcs = 0x40, /* IP Checksum Calculated on Packet */`
		343	`Pif = 0x80, /* Passed in-exact filter */`
		344	`};`
		345
		346	`enum { /* Rd errors */`
		347	`Ce = 0x01, /* CRC Error or Alignment Error */`
		348	`Se = 0x02, /* Symbol Error */`
		349	`Seq = 0x04, /* Sequence Error */`
		350	`Cxe = 0x10, /* Carrier Extension Error */`
		351	`Tcpe = 0x20, /* TCP/UDP Checksum Error */`
		352	`Ipe = 0x40, /* IP Checksum Error */`
		353	`Rxe = 0x80, /* RX Data Error */`
		354	`};`
		355
		356	`struct Td { /* Transmit Descriptor */`
		357	`u32int addr[2]; /* Data */`
		358	`u32int control;`
		359	`u32int status;`
		360	`};`
		361
		362	`enum { /* Tdesc control */`
		363	`LenMASK = 0x000FFFFF, /* Data/Packet Length Field */`
		364	`LenSHIFT = 0,`
		365	`DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */`
		366	`DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */`
		367	`PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */`
		368	`Teop = 0x01000000, /* End of Packet (DD) */`
		369	`PtypeIP = 0x02000000, /* IP Packet Type (CD) */`
		370	`Ifcs = 0x02000000, /* Insert FCS (DD) */`
		371	`Tse = 0x04000000, /* TCP Segmentation Enable */`
		372	`Rs = 0x08000000, /* Report Status */`
		373	`Rps = 0x10000000, /* Report Status Sent */`
		374	`Dext = 0x20000000, /* Descriptor Extension */`
		375	`Vle = 0x40000000, /* VLAN Packet Enable */`
		376	`Ide = 0x80000000, /* Interrupt Delay Enable */`
		377	`};`
		378
		379	`enum { /* Tdesc status */`
		380	`Tdd = 0x0001, /* Descriptor Done */`
		381	`Ec = 0x0002, /* Excess Collisions */`
		382	`Lc = 0x0004, /* Late Collision */`
		383	`Tu = 0x0008, /* Transmit Underrun */`
		384	`CssMASK = 0xFF00, /* Checksum Start Field */`
		385	`CssSHIFT = 8,`
		386	`};`
		387
		388	`typedef struct {`
		389	`u16int *reg;`
		390	`u32int *reg32;`
		391	`u16int base;`
		392	`u16int lim;`
		393	`} Flash;`
		394
		395	`enum {`
		396	`/* 16 and 32-bit flash registers for ich flash parts */`
		397	`Bfpr = 0x00/4, /* flash base 0:12; lim 16:28 */`
		398	`Fsts = 0x04/2, /* flash status; Hsfsts */`
		399	`Fctl = 0x06/2, /* flash control; Hsfctl */`
		400	`Faddr = 0x08/4, /* flash address to r/w */`
		401	`Fdata = 0x10/4, /* data @ address */`
		402
		403	`/* status register */`
		404	`Fdone = 1<<0, /* flash cycle done */`
		405	`Fcerr = 1<<1, /* cycle error; write 1 to clear */`
		406	`Ael = 1<<2, /* direct access error log; 1 to clear */`
		407	`Scip = 1<<5, /* spi cycle in progress */`
		408	`Fvalid = 1<<14, /* flash descriptor valid */`
		409
		410	`/* control register */`
		411	`Fgo = 1<<0, /* start cycle */`
		412	`Flcycle = 1<<1, /* two bits: r=0; w=2 */`
		413	`Fdbc = 1<<8, /* bytes to read; 5 bits */`
		414	`};`
		415
		416	`enum {`
		417	`/* were 512, 1024 & 64, but 52, 253 and 9 are ample. */`
		418	`Nrd = 128, /* power of two */`
		419	`Nrb = 512, /* private receive buffers per Ctlr */`
		420	`Ntd = 32, /* power of two */`
		421	`};`
		422
		423	`enum {`
		424	`Iany,`
		425	`i82563,`
		426	`i82566,`
		427	`i82567,`
		428	`i82571,`
		429	`i82572,`
		430	`i82573,`
		431	`i82574,`
		432	`i82575,`
		433	`i82576,`
		434	`i82577,`
		435	`i82579,`
		436	`};`
		437
		438	`static int rbtab[] = {`
		439	`0,`
		440	`9014,`
		441	`ETHERMAXTU,`
		442	`ETHERMAXTU,`
		443	`9234,`
		444	`9234,`
		445	`8192, /* terrible performance above 8k */`
		446	`ETHERMAXTU,`
		447	`ETHERMAXTU,`
		448	`ETHERMAXTU,`
		449	`ETHERMAXTU,`
		450	`9018,`
		451	`};`
		452
		453	`static char *tname[] = {`
		454	`"any",`
		455	`"i82563",`
		456	`"i82566",`
		457	`"i82567",`
		458	`"i82571",`
		459	`"i82572",`
		460	`"i82573",`
		461	`"i82574",`
		462	`"i82575",`
		463	`"i82576",`
		464	`"i82577",`
		465	`"i82579",`
		466	`};`
		467
		468	`struct Ctlr {`
		469	`int port;`
		470	`Pcidev *pcidev;`
		471	`Ctlr *next;`
		472	`Ether *edev;`
		473	`int active;`
		474	`int type;`
		475	`ushort eeprom[0x40];`
		476
		477	`QLock alock; /* attach */`
		478	`int attached;`
		479	`int nrd;`
		480	`int ntd;`
		481	`int nrb; /* # rcv bufs this Ctlr has in the pool */`
		482	`unsigned rbsz; /* unsigned for % and / by 1024 */`
		483
		484	`int *nic;`
		485	`Lock imlock;`
		486	`int im; /* interrupt mask */`
		487
		488	`Rendez lrendez;`
		489	`int lim;`
		490
		491	`Watermark wmrb;`
		492	`Watermark wmrd;`
		493	`Watermark wmtd;`
		494
		495	`QLock slock;`
		496	`uint statistics[Nstatistics];`
		497	`uint lsleep;`
		498	`uint lintr;`
		499	`uint rsleep;`
		500	`uint rintr;`
		501	`uint txdw;`
		502	`uint tintr;`
		503	`uint ixsm;`
		504	`uint ipcs;`
		505	`uint tcpcs;`
		506	`uint speeds[4];`
		507
		508	`uchar ra[Eaddrlen]; /* receive address */`
		509	`ulong mta[128]; /* multicast table array */`
		510
		511	`Rendez rrendez;`
		512	`int rim;`
		513	`int rdfree; /* rx descriptors awaiting packets */`
		514	`Rd rdba; / receive descriptor base address */`
		515	`Block *rb; / receive buffers */`
		516	`int rdh; /* receive descriptor head */`
		517	`int rdt; /* receive descriptor tail */`
		518	`int rdtr; /* receive delay timer ring value */`
		519	`int radv; /* receive interrupt absolute delay timer */`
		520
		521	`Rendez trendez;`
		522	`QLock tlock;`
		523	`Td tdba; / transmit descriptor base address */`
		524	`Block *tb; / transmit buffers */`
		525	`int tdh; /* transmit descriptor head */`
		526	`int tdt; /* transmit descriptor tail */`
		527
		528	`int fcrtl;`
		529	`int fcrth;`
		530
		531	`uint pba; /* packet buffer allocation */`
		532	`};`
		533
		534	`#define csr32r(c, r) (*((c)->nic+((r)/4)))`
		535	`#define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))`
		536
		537	`static Ctlr* i82563ctlrhead;`
		538	`static Ctlr* i82563ctlrtail;`
		539
		540	`static Lock i82563rblock; /* free receive Blocks */`
		541	`static Block* i82563rbpool;`
		542	`static int nrbfull; /* # of rcv Blocks with data awaiting processing */`
		543
		544	`static char* statistics[] = {`
		545	`"CRC Error",`
		546	`"Alignment Error",`
		547	`"Symbol Error",`
		548	`"RX Error",`
		549	`"Missed Packets",`
		550	`"Single Collision",`
		551	`"Excessive Collisions",`
		552	`"Multiple Collision",`
		553	`"Late Collisions",`
		554	`nil,`
		555	`"Collision",`
		556	`"Transmit Underrun",`
		557	`"Defer",`
		558	`"Transmit - No CRS",`
		559	`"Sequence Error",`
		560	`"Carrier Extension Error",`
		561	`"Receive Error Length",`
		562	`nil,`
		563	`"XON Received",`
		564	`"XON Transmitted",`
		565	`"XOFF Received",`
		566	`"XOFF Transmitted",`
		567	`"FC Received Unsupported",`
		568	`"Packets Received (64 Bytes)",`
		569	`"Packets Received (65-127 Bytes)",`
		570	`"Packets Received (128-255 Bytes)",`
		571	`"Packets Received (256-511 Bytes)",`
		572	`"Packets Received (512-1023 Bytes)",`
		573	`"Packets Received (1024-mtu Bytes)",`
		574	`"Good Packets Received",`
		575	`"Broadcast Packets Received",`
		576	`"Multicast Packets Received",`
		577	`"Good Packets Transmitted",`
		578	`nil,`
		579	`"Good Octets Received",`
		580	`nil,`
		581	`"Good Octets Transmitted",`
		582	`nil,`
		583	`nil,`
		584	`nil,`
		585	`"Receive No Buffers",`
		586	`"Receive Undersize",`
		587	`"Receive Fragment",`
		588	`"Receive Oversize",`
		589	`"Receive Jabber",`
		590	`"Management Packets Rx",`
		591	`"Management Packets Drop",`
		592	`"Management Packets Tx",`
		593	`"Total Octets Received",`
		594	`nil,`
		595	`"Total Octets Transmitted",`
		596	`nil,`
		597	`"Total Packets Received",`
		598	`"Total Packets Transmitted",`
		599	`"Packets Transmitted (64 Bytes)",`
		600	`"Packets Transmitted (65-127 Bytes)",`
		601	`"Packets Transmitted (128-255 Bytes)",`
		602	`"Packets Transmitted (256-511 Bytes)",`
		603	`"Packets Transmitted (512-1023 Bytes)",`
		604	`"Packets Transmitted (1024-mtu Bytes)",`
		605	`"Multicast Packets Transmitted",`
		606	`"Broadcast Packets Transmitted",`
		607	`"TCP Segmentation Context Transmitted",`
		608	`"TCP Segmentation Context Fail",`
		609	`"Interrupt Assertion",`
		610	`"Interrupt Rx Pkt Timer",`
		611	`"Interrupt Rx Abs Timer",`
		612	`"Interrupt Tx Pkt Timer",`
		613	`"Interrupt Tx Abs Timer",`
		614	`"Interrupt Tx Queue Empty",`
		615	`"Interrupt Tx Desc Low",`
		616	`"Interrupt Rx Min",`
		617	`"Interrupt Rx Overrun",`
		618	`};`
		619
		620	`static long`
		621	`i82563ifstat(Ether* edev, void* a, long n, ulong offset)`
		622	`{`
		623	`Ctlr *ctlr;`
		624	`char s, p, e, stat;`
		625	`int i, r;`
		626	`uvlong tuvl, ruvl;`
		627
		628	`ctlr = edev->ctlr;`
		629	`qlock(&ctlr->slock);`
		630	`p = s = malloc(READSTR);`
		631	`if(p == nil) {`
		632	`qunlock(&ctlr->slock);`
		633	`error(Enomem);`
		634	`}`
		635	`e = p + READSTR;`
		636
		637	`for(i = 0; i < Nstatistics; i++){`
		638	`r = csr32r(ctlr, Statistics + i*4);`
		639	`if((stat = statistics[i]) == nil)`
		640	`continue;`
		641	`switch(i){`
		642	`case Gorcl:`
		643	`case Gotcl:`
		644	`case Torl:`
		645	`case Totl:`
		646	`ruvl = r;`
		647	`ruvl += (uvlong)csr32r(ctlr, Statistics+(i+1)*4) << 32;`
		648	`tuvl = ruvl;`
		649	`tuvl += ctlr->statistics[i];`
		650	`tuvl += (uvlong)ctlr->statistics[i+1] << 32;`
		651	`if(tuvl == 0)`
		652	`continue;`
		653	`ctlr->statistics[i] = tuvl;`
		654	`ctlr->statistics[i+1] = tuvl >> 32;`
		655	`p = seprint(p, e, "%s: %llud %llud\n", stat, tuvl, ruvl);`
		656	`i++;`
		657	`break;`
		658
		659	`default:`
		660	`ctlr->statistics[i] += r;`
		661	`if(ctlr->statistics[i] == 0)`
		662	`continue;`
		663	`p = seprint(p, e, "%s: %ud %ud\n", stat,`
		664	`ctlr->statistics[i], r);`
		665	`break;`
		666	`}`
		667	`}`
		668
		669	`p = seprint(p, e, "lintr: %ud %ud\n", ctlr->lintr, ctlr->lsleep);`
		670	`p = seprint(p, e, "rintr: %ud %ud\n", ctlr->rintr, ctlr->rsleep);`
		671	`p = seprint(p, e, "tintr: %ud %ud\n", ctlr->tintr, ctlr->txdw);`
		672	`p = seprint(p, e, "ixcs: %ud %ud %ud\n", ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);`
		673	`p = seprint(p, e, "rdtr: %ud\n", ctlr->rdtr);`
		674	`p = seprint(p, e, "radv: %ud\n", ctlr->radv);`
		675	`p = seprint(p, e, "ctrl: %.8ux\n", csr32r(ctlr, Ctrl));`
		676	`p = seprint(p, e, "ctrlext: %.8ux\n", csr32r(ctlr, Ctrlext));`
		677	`p = seprint(p, e, "status: %.8ux\n", csr32r(ctlr, Status));`
		678	`p = seprint(p, e, "txcw: %.8ux\n", csr32r(ctlr, Txcw));`
		679	`p = seprint(p, e, "txdctl: %.8ux\n", csr32r(ctlr, Txdctl));`
		680	`p = seprint(p, e, "pba: %.8ux\n", ctlr->pba);`
		681
		682	`p = seprint(p, e, "speeds: 10:%ud 100:%ud 1000:%ud ?:%ud\n",`
		683	`ctlr->speeds[0], ctlr->speeds[1], ctlr->speeds[2], ctlr->speeds[3]);`
		684	`p = seprint(p, e, "type: %s\n", tname[ctlr->type]);`
		685	`p = seprint(p, e, "nrbfull (rcv blocks outstanding): %d\n", nrbfull);`
		686
		687	`// p = seprint(p, e, "eeprom:");`
		688	`// for(i = 0; i < 0x40; i++){`
		689	`// if(i && ((i & 7) == 0))`
		690	`// p = seprint(p, e, "\n ");`
		691	`// p = seprint(p, e, " %4.4ux", ctlr->eeprom[i]);`
		692	`// }`
		693	`// p = seprint(p, e, "\n");`
		694
		695	`p = seprintmark(p, e, &ctlr->wmrb);`
		696	`p = seprintmark(p, e, &ctlr->wmrd);`
		697	`p = seprintmark(p, e, &ctlr->wmtd);`
		698
		699	`USED(p);`
		700	`n = readstr(offset, a, n, s);`
		701	`free(s);`
		702	`qunlock(&ctlr->slock);`
		703
		704	`return n;`
		705	`}`
		706
		707	`enum {`
		708	`CMrdtr,`
		709	`CMradv,`
		710	`};`
		711
		712	`static Cmdtab i82563ctlmsg[] = {`
		713	`CMrdtr, "rdtr", 2,`
		714	`CMradv, "radv", 2,`
		715	`};`
		716
		717	`static long`
		718	`i82563ctl(Ether* edev, void* buf, long n)`
		719	`{`
		720	`ulong v;`
		721	`char *p;`
		722	`Ctlr *ctlr;`
		723	`Cmdbuf *cb;`
		724	`Cmdtab *ct;`
		725
		726	`if((ctlr = edev->ctlr) == nil)`
		727	`error(Enonexist);`
		728
		729	`cb = parsecmd(buf, n);`
		730	`if(waserror()){`
		731	`free(cb);`
		732	`nexterror();`
		733	`}`
		734
		735	`ct = lookupcmd(cb, i82563ctlmsg, nelem(i82563ctlmsg));`
		736	`switch(ct->index){`
		737	`case CMrdtr:`
		738	`v = strtoul(cb->f[1], &p, 0);`
		739	`if(p == cb->f[1] \|\| v > 0xFFFF)`
		740	`error(Ebadarg);`
		741	`ctlr->rdtr = v;`
		742	`csr32w(ctlr, Rdtr, v);`
		743	`break;`
		744	`case CMradv:`
		745	`v = strtoul(cb->f[1], &p, 0);`
		746	`if(p == cb->f[1] \|\| v > 0xFFFF)`
		747	`error(Ebadarg);`
		748	`ctlr->radv = v;`
		749	`csr32w(ctlr, Radv, v);`
		750	`}`
		751	`free(cb);`
		752	`poperror();`
		753
		754	`return n;`
		755	`}`
		756
		757	`static void`
		758	`i82563promiscuous(void* arg, int on)`
		759	`{`
		760	`int rctl;`
		761	`Ctlr *ctlr;`
		762	`Ether *edev;`
		763
		764	`edev = arg;`
		765	`ctlr = edev->ctlr;`
		766
		767	`rctl = csr32r(ctlr, Rctl);`
		768	`rctl &= ~MoMASK;`
		769	`if(on)`
		770	`rctl \|= Upe\|Mpe;`
		771	`else`
		772	`rctl &= ~(Upe\|Mpe);`
		773	`csr32w(ctlr, Rctl, rctl);`
		774	`}`
		775
		776	`static void`
		777	`i82563multicast(void* arg, uchar* addr, int on)`
		778	`{`
		779	`int bit, x;`
		780	`Ctlr *ctlr;`
		781	`Ether *edev;`
		782
		783	`edev = arg;`
		784	`ctlr = edev->ctlr;`
		785
		786	`x = addr[5]>>1;`
		787	`if(ctlr->type == i82566 \|\| ctlr->type == i82567)`
		788	`x &= 31;`
		789	`bit = ((addr[5] & 1)<<4)\|(addr[4]>>4);`
		790	`/*`
		791	`* multiple ether addresses can hash to the same filter bit,`
		792	`* so it's never safe to clear a filter bit.`
		793	`* if we want to clear filter bits, we need to keep track of`
		794	`* all the multicast addresses in use, clear all the filter bits,`
		795	`* then set the ones corresponding to in-use addresses.`
		796	`*/`
		797	`if(on)`
		798	`ctlr->mta[x] \|= 1<<bit;`
		799	`// else`
		800	`// ctlr->mta[x] &= ~(1<<bit);`
		801
		802	`csr32w(ctlr, Mta+x*4, ctlr->mta[x]);`
		803	`}`
		804
		805	`static Block*`
		806	`i82563rballoc(void)`
		807	`{`
		808	`Block *bp;`
		809
		810	`ilock(&i82563rblock);`
		811	`if((bp = i82563rbpool) != nil){`
		812	`i82563rbpool = bp->next;`
		813	`bp->next = nil;`
		814	`_xinc(&bp->ref); /* prevent bp from being freed */`
		815	`}`
		816	`iunlock(&i82563rblock);`
		817
		818	`return bp;`
		819	`}`
		820
		821	`static void`
		822	`i82563rbfree(Block* b)`
		823	`{`
		824	`b->rp = b->wp = (uchar*)PGROUND((uintptr)b->base);`
		825	`b->flag &= ~(Bipck \| Budpck \| Btcpck \| Bpktck);`
		826	`ilock(&i82563rblock);`
		827	`b->next = i82563rbpool;`
		828	`i82563rbpool = b;`
		829	`nrbfull--;`
		830	`iunlock(&i82563rblock);`
		831	`}`
		832
		833	`static void`
		834	`i82563im(Ctlr* ctlr, int im)`
		835	`{`
		836	`ilock(&ctlr->imlock);`
		837	`ctlr->im \|= im;`
		838	`csr32w(ctlr, Ims, ctlr->im);`
		839	`iunlock(&ctlr->imlock);`
		840	`}`
		841
		842	`static void`
		843	`i82563txinit(Ctlr* ctlr)`
		844	`{`
		845	`int i, r;`
		846	`Block *bp;`
		847
		848	`csr32w(ctlr, Tctl, 0x0F<<CtSHIFT \| Psp \| 66<<ColdSHIFT \| Mulr);`
		849	`csr32w(ctlr, Tipg, 6<<20 \| 8<<10 \| 8); /* yb sez: 0x702008 */`
		850	`csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));`
		851	`csr32w(ctlr, Tdbah, 0);`
		852	`csr32w(ctlr, Tdlen, ctlr->ntd * sizeof(Td));`
		853	`ctlr->tdh = PREV(0, ctlr->ntd);`
		854	`csr32w(ctlr, Tdh, 0);`
		855	`ctlr->tdt = 0;`
		856	`csr32w(ctlr, Tdt, 0);`
		857	`for(i = 0; i < ctlr->ntd; i++){`
		858	`if((bp = ctlr->tb[i]) != nil){`
		859	`ctlr->tb[i] = nil;`
		860	`freeb(bp);`
		861	`}`
		862	`memset(&ctlr->tdba[i], 0, sizeof(Td));`
		863	`}`
		864	`csr32w(ctlr, Tidv, 128);`
		865	`r = csr32r(ctlr, Txdctl);`
		866	`r &= ~(WthreshMASK\|PthreshMASK);`
		867	`r \|= 4<<WthreshSHIFT \| 4<<PthreshSHIFT;`
		868	`if(ctlr->type == i82575 \|\| ctlr->type == i82576)`
		869	`r \|= Qenable;`
		870	`csr32w(ctlr, Tadv, 64);`
		871	`csr32w(ctlr, Txdctl, r);`
		872	`r = csr32r(ctlr, Tctl);`
		873	`r \|= Ten;`
		874	`csr32w(ctlr, Tctl, r);`
		875	`// if(ctlr->type == i82671)`
		876	`// csr32w(ctlr, Tarc0, csr32r(ctlr, Tarc0) \| 7<<24); /* yb sez? */`
		877	`}`
		878
		879	`#define Next(x, m) (((x)+1) & (m))`
		880
		881	`static int`
		882	`i82563cleanup(Ctlr *ctlr)`
		883	`{`
		884	`Block *b;`
		885	`int tdh, m, n;`
		886
		887	`tdh = ctlr->tdh;`
		888	`m = ctlr->ntd-1;`
		889	`while(ctlr->tdba[n = Next(tdh, m)].status & Tdd){`
		890	`tdh = n;`
		891	`if((b = ctlr->tb[tdh]) != nil){`
		892	`ctlr->tb[tdh] = nil;`
		893	`freeb(b);`
		894	`}else`
		895	`iprint("82563 tx underrun!\n");`
		896	`ctlr->tdba[tdh].status = 0;`
		897	`}`
		898
		899	`return ctlr->tdh = tdh;`
		900	`}`
		901
		902	`static void`
		903	`i82563transmit(Ether* edev)`
		904	`{`
		905	`Td *td;`
		906	`Block *bp;`
		907	`Ctlr *ctlr;`
		908	`int tdh, tdt, m;`
		909
		910	`ctlr = edev->ctlr;`
		911
		912	`qlock(&ctlr->tlock);`
		913
		914	`/*`
		915	`* Free any completed packets`
		916	`*/`
		917	`tdh = i82563cleanup(ctlr);`
		918
		919	`/*`
		920	`* Try to fill the ring back up.`
		921	`*/`
		922	`tdt = ctlr->tdt;`
		923	`m = ctlr->ntd-1;`
		924	`for(;;){`
		925	`if(Next(tdt, m) == tdh){`
		926	`ctlr->txdw++;`
		927	`i82563im(ctlr, Txdw);`
		928	`break;`
		929	`}`
		930	`if((bp = qget(edev->oq)) == nil)`
		931	`break;`
		932	`td = &ctlr->tdba[tdt];`
		933	`td->addr[0] = PCIWADDR(bp->rp);`
		934	`td->control = Ide\|Rs\|Ifcs\|Teop\|BLEN(bp);`
		935	`ctlr->tb[tdt] = bp;`
		936	`/* note size of queue of tds awaiting transmission */`
		937	`notemark(&ctlr->wmtd, (tdt + Ntd - tdh) % Ntd);`
		938	`tdt = Next(tdt, m);`
		939	`}`
		940	`if(ctlr->tdt != tdt){`
		941	`ctlr->tdt = tdt;`
		942	`csr32w(ctlr, Tdt, tdt);`
		943	`}`
		944	`qunlock(&ctlr->tlock);`
		945	`}`
		946
		947	`static void`
		948	`i82563replenish(Ctlr* ctlr)`
		949	`{`
		950	`Rd *rd;`
		951	`int rdt, m;`
		952	`Block *bp;`
		953
		954	`rdt = ctlr->rdt;`
		955	`m = ctlr->nrd-1;`
		956	`while(Next(rdt, m) != ctlr->rdh){`
		957	`rd = &ctlr->rdba[rdt];`
		958	`if(ctlr->rb[rdt] != nil){`
		959	`print("#l%d: 82563: rx overrun\n", ctlr->edev->ctlrno);`
		960	`break;`
		961	`}`
		962	`bp = i82563rballoc();`
		963	`if(bp == nil)`
		964	`/*`
		965	`* this almost never gets better. likely there's a bug`
		966	`* elsewhere in the kernel that is failing to free a`
		967	`* receive Block.`
		968	`*/`
		969	`panic("#l%d: 82563: all %d rx buffers in use, nrbfull %d",`
		970	`ctlr->edev->ctlrno, ctlr->nrb, nrbfull);`
		971	`ctlr->rb[rdt] = bp;`
		972	`rd->addr[0] = PCIWADDR(bp->rp);`
		973	`// rd->addr[1] = 0;`
		974	`rd->status = 0;`
		975	`ctlr->rdfree++;`
		976	`rdt = Next(rdt, m);`
		977	`}`
		978	`ctlr->rdt = rdt;`
		979	`csr32w(ctlr, Rdt, rdt);`
		980	`}`
		981
		982	`static void`
		983	`i82563rxinit(Ctlr* ctlr)`
		984	`{`
		985	`Block *bp;`
		986	`int i, r, rctl;`
		987
		988	`if(ctlr->rbsz <= 2048)`
		989	`rctl = Dpf\|Bsize2048\|Bam\|RdtmsHALF;`
		990	`else if(ctlr->rbsz <= 8192)`
		991	`rctl = Lpe\|Dpf\|Bsize8192\|Bsex\|Bam\|RdtmsHALF\|Secrc;`
		992	`else if(ctlr->rbsz <= 12*1024){`
		993	`i = ctlr->rbsz / 1024;`
		994	`if(ctlr->rbsz % 1024)`
		995	`i++;`
		996	`rctl = Lpe\|Dpf\|BsizeFlex*i\|Bam\|RdtmsHALF\|Secrc;`
		997	`}`
		998	`else`
		999	`rctl = Lpe\|Dpf\|Bsize16384\|Bsex\|Bam\|RdtmsHALF\|Secrc;`
		1000
		1001	`if(ctlr->type == i82575 \|\| ctlr->type == i82576){`
		1002	`/*`
		1003	`* Setting Qenable in Rxdctl does not`
		1004	`* appear to stick unless Ren is on.`
		1005	`*/`
		1006	`csr32w(ctlr, Rctl, Ren\|rctl);`
		1007	`r = csr32r(ctlr, Rxdctl);`
		1008	`r \|= Qenable;`
		1009	`csr32w(ctlr, Rxdctl, r);`
		1010	`}`
		1011	`csr32w(ctlr, Rctl, rctl);`
		1012
		1013	`if(ctlr->type == i82573 \|\| ctlr->type == i82577 \|\| ctlr->type == i82579)`
		1014	`csr32w(ctlr, Ert, 1024/8);`
		1015
		1016	`if(ctlr->type == i82566 \|\| ctlr->type == i82567)`
		1017	`csr32w(ctlr, Pbs, 16);`
		1018
		1019	`csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));`
		1020	`csr32w(ctlr, Rdbah, 0);`
		1021	`csr32w(ctlr, Rdlen, ctlr->nrd * sizeof(Rd));`
		1022	`ctlr->rdh = 0;`
		1023	`csr32w(ctlr, Rdh, 0);`
		1024	`ctlr->rdt = 0;`
		1025	`csr32w(ctlr, Rdt, 0);`
		1026	`/* to hell with interrupt moderation, we've got fast cpus */`
		1027	`// ctlr->rdtr = 25; /* µs units? */`
		1028	`// ctlr->radv = 500; /* µs units? */`
		1029	`ctlr->radv = ctlr->rdtr = 0;`
		1030	`csr32w(ctlr, Rdtr, ctlr->rdtr);`
		1031	`csr32w(ctlr, Radv, ctlr->radv);`
		1032
		1033	`for(i = 0; i < ctlr->nrd; i++){`
		1034	`if((bp = ctlr->rb[i]) != nil){`
		1035	`ctlr->rb[i] = nil;`
		1036	`freeb(bp);`
		1037	`}`
		1038	`}`
		1039	`i82563replenish(ctlr);`
		1040
		1041	`if(ctlr->type != i82575 \|\| ctlr->type == i82576){`
		1042	`/*`
		1043	`* See comment above for Qenable.`
		1044	`* Could shuffle the code?`
		1045	`*/`
		1046	`r = csr32r(ctlr, Rxdctl);`
		1047	`r &= ~(WthreshMASK\|PthreshMASK);`
		1048	`r \|= (2<<WthreshSHIFT)\|(2<<PthreshSHIFT);`
		1049	`csr32w(ctlr, Rxdctl, r);`
		1050	`}`
		1051
		1052	`/*`
		1053	`* Don't enable checksum offload. In practice, it interferes with`
		1054	`* tftp booting on at least the 82575.`
		1055	`*/`
		1056	`// csr32w(ctlr, Rxcsum, Tuofl \| Ipofl \| ETHERHDRSIZE<<PcssSHIFT);`
		1057	`csr32w(ctlr, Rxcsum, 0);`
		1058	`}`
		1059
		1060	`static int`
		1061	`i82563rim(void* ctlr)`
		1062	`{`
		1063	`return ((Ctlr*)ctlr)->rim != 0;`
		1064	`}`
		1065
		1066	`static void`
		1067	`i82563rproc(void* arg)`
		1068	`{`
		1069	`Rd *rd;`
		1070	`Block *bp;`
		1071	`Ctlr *ctlr;`
		1072	`int r, m, rdh, rim, passed;`
		1073	`Ether *edev;`
		1074
		1075	`edev = arg;`
		1076	`ctlr = edev->ctlr;`
		1077
		1078	`i82563rxinit(ctlr);`
		1079	`r = csr32r(ctlr, Rctl);`
		1080	`r \|= Ren;`
		1081	`csr32w(ctlr, Rctl, r);`
		1082	`m = ctlr->nrd-1;`
		1083
		1084	`for(;;){`
		1085	`i82563replenish(ctlr);`
		1086	`i82563im(ctlr, Rxt0\|Rxo\|Rxdmt0\|Rxseq\|Ack);`
		1087	`ctlr->rsleep++;`
		1088	`sleep(&ctlr->rrendez, i82563rim, ctlr);`
		1089
		1090	`rdh = ctlr->rdh;`
		1091	`passed = 0;`
		1092	`for(;;){`
		1093	`rim = ctlr->rim;`
		1094	`ctlr->rim = 0;`
		1095	`rd = &ctlr->rdba[rdh];`
		1096	`if(!(rd->status & Rdd))`
		1097	`break;`
		1098
		1099	`/*`
		1100	`* Accept eop packets with no errors.`
		1101	`* With no errors and the Ixsm bit set,`
		1102	`* the descriptor status Tpcs and Ipcs bits give`
		1103	`* an indication of whether the checksums were`
		1104	`* calculated and valid.`
		1105	`*/`
		1106	`bp = ctlr->rb[rdh];`
		1107	`if((rd->status & Reop) && rd->errors == 0){`
		1108	`bp->wp += rd->length;`
		1109	`bp->lim = bp->wp; /* lie like a dog. */`
		1110	`if(!(rd->status & Ixsm)){`
		1111	`ctlr->ixsm++;`
		1112	`if(rd->status & Ipcs){`
		1113	`/*`
		1114	`* IP checksum calculated`
		1115	`* (and valid as errors == 0).`
		1116	`*/`
		1117	`ctlr->ipcs++;`
		1118	`bp->flag \|= Bipck;`
		1119	`}`
		1120	`if(rd->status & Tcpcs){`
		1121	`/*`
		1122	`* TCP/UDP checksum calculated`
		1123	`* (and valid as errors == 0).`
		1124	`*/`
		1125	`ctlr->tcpcs++;`
		1126	`bp->flag \|= Btcpck\|Budpck;`
		1127	`}`
		1128	`bp->checksum = rd->checksum;`
		1129	`bp->flag \|= Bpktck;`
		1130	`}`
		1131	`ilock(&i82563rblock);`
		1132	`nrbfull++;`
		1133	`iunlock(&i82563rblock);`
		1134	`notemark(&ctlr->wmrb, nrbfull);`
		1135	`etheriq(edev, bp, 1);`
		1136	`passed++;`
		1137	`} else {`
		1138	`if (rd->status & Reop && rd->errors)`
		1139	`print("%s: input packet error %#ux\n",`
		1140	`tname[ctlr->type], rd->errors);`
		1141	`freeb(bp);`
		1142	`}`
		1143	`ctlr->rb[rdh] = nil;`
		1144
		1145	`/* rd needs to be replenished to accept another pkt */`
		1146	`rd->status = 0;`
		1147	`ctlr->rdfree--;`
		1148	`ctlr->rdh = rdh = Next(rdh, m);`
		1149	`/*`
		1150	`* if number of rds ready for packets is too low,`
		1151	`* set up the unready ones.`
		1152	`*/`
		1153	`if(ctlr->rdfree <= ctlr->nrd - 32 \|\| (rim & Rxdmt0))`
		1154	`i82563replenish(ctlr);`
		1155	`}`
		1156	`/* note how many rds had full buffers */`
		1157	`notemark(&ctlr->wmrd, passed);`
		1158	`}`
		1159	`}`
		1160
		1161	`static int`
		1162	`i82563lim(void* ctlr)`
		1163	`{`
		1164	`return ((Ctlr*)ctlr)->lim != 0;`
		1165	`}`
		1166
		1167	`static int speedtab[] = {`
		1168	`10, 100, 1000, 0`
		1169	`};`
		1170
		1171	`static uint`
		1172	`phyread(Ctlr *ctlr, int reg)`
		1173	`{`
		1174	`uint phy, i;`
		1175
		1176	`csr32w(ctlr, Mdic, MDIrop \| 1<<MDIpSHIFT \| reg<<MDIrSHIFT);`
		1177	`phy = 0;`
		1178	`for(i = 0; i < 64; i++){`
		1179	`phy = csr32r(ctlr, Mdic);`
		1180	`if(phy & (MDIe\|MDIready))`
		1181	`break;`
		1182	`microdelay(1);`
		1183	`}`
		1184	`if((phy & (MDIe\|MDIready)) != MDIready)`
		1185	`return ~0;`
		1186	`return phy & 0xffff;`
		1187	`}`
		1188
		1189	`static uint`
		1190	`phywrite(Ctlr *ctlr, int reg, ushort val)`
		1191	`{`
		1192	`uint phy, i;`
		1193
		1194	`csr32w(ctlr, Mdic, MDIwop \| 1<<MDIpSHIFT \| reg<<MDIrSHIFT \| val);`
		1195	`phy = 0;`
		1196	`for(i = 0; i < 64; i++){`
		1197	`phy = csr32r(ctlr, Mdic);`
		1198	`if(phy & (MDIe\|MDIready))`
		1199	`break;`
		1200	`microdelay(1);`
		1201	`}`
		1202	`if((phy & (MDIe\|MDIready)) != MDIready)`
		1203	`return ~0;`
		1204	`return 0;`
		1205	`}`
		1206
		1207	`/*`
		1208	`* watch for changes of link state`
		1209	`*/`
		1210	`static void`
		1211	`i82563lproc(void *v)`
		1212	`{`
		1213	`uint phy, i, a;`
		1214	`Ctlr *ctlr;`
		1215	`Ether *e;`
		1216
		1217	`e = v;`
		1218	`ctlr = e->ctlr;`
		1219
		1220	`if(ctlr->type == i82573 && (phy = phyread(ctlr, Phyier)) != ~0)`
		1221	`phywrite(ctlr, Phyier, phy \| Lscie \| Ancie \| Spdie \| Panie);`
		1222	`for(;;){`
		1223	`phy = phyread(ctlr, Physsr);`
		1224	`if(phy == ~0)`
		1225	`goto next;`
		1226	`i = (phy>>14) & 3;`
		1227
		1228	`switch(ctlr->type){`
		1229	`case i82563:`
		1230	`a = phyread(ctlr, Phyisr) & Ane;`
		1231	`break;`
		1232	`case i82571:`
		1233	`case i82572:`
		1234	`case i82575:`
		1235	`case i82576:`
		1236	`a = phyread(ctlr, Phylhr) & Anf;`
		1237	`i = (i-1) & 3;`
		1238	`break;`
		1239	`default:`
		1240	`a = 0;`
		1241	`break;`
		1242	`}`
		1243	`if(a)`
		1244	`phywrite(ctlr, Phyctl, phyread(ctlr, Phyctl) \| Ran \| Ean);`
		1245	`e->link = (phy & Rtlink) != 0;`
		1246	`if(e->link){`
		1247	`ctlr->speeds[i]++;`
		1248	`if (speedtab[i])`
		1249	`e->mbps = speedtab[i];`
		1250	`}`
		1251	`next:`
		1252	`ctlr->lim = 0;`
		1253	`i82563im(ctlr, Lsc);`
		1254	`ctlr->lsleep++;`
		1255	`sleep(&ctlr->lrendez, i82563lim, ctlr);`
		1256	`}`
		1257	`}`
		1258
		1259	`static void`
		1260	`i82563tproc(void *v)`
		1261	`{`
		1262	`Ether *e;`
		1263	`Ctlr *ctlr;`
		1264
		1265	`e = v;`
		1266	`ctlr = e->ctlr;`
		1267	`for(;;){`
		1268	`sleep(&ctlr->trendez, return0, 0);`
		1269	`i82563transmit(e);`
		1270	`}`
		1271	`}`
		1272
		1273	`static void`
		1274	`i82563attach(Ether* edev)`
		1275	`{`
		1276	`Block *bp;`
		1277	`Ctlr *ctlr;`
		1278	`char name[KNAMELEN];`
		1279
		1280	`ctlr = edev->ctlr;`
		1281	`qlock(&ctlr->alock);`
		1282	`if(ctlr->attached){`
		1283	`qunlock(&ctlr->alock);`
		1284	`return;`
		1285	`}`
		1286
		1287	`ctlr->nrd = Nrd;`
		1288	`ctlr->ntd = Ntd;`
		1289
		1290	`if(waserror()){`
		1291	`while(ctlr->nrb > 0){`
		1292	`bp = i82563rballoc();`
		1293	`bp->free = nil;`
		1294	`freeb(bp);`
		1295	`ctlr->nrb--;`
		1296	`}`
		1297	`free(ctlr->tb);`
		1298	`ctlr->tb = nil;`
		1299	`free(ctlr->rb);`
		1300	`ctlr->rb = nil;`
		1301	`free(ctlr->tdba);`
		1302	`ctlr->tdba = nil;`
		1303	`free(ctlr->rdba);`
		1304	`ctlr->rdba = nil;`
		1305	`qunlock(&ctlr->alock);`
		1306	`nexterror();`
		1307	`}`
		1308
		1309	`if((ctlr->rdba = mallocalign(ctlr->nrd*sizeof(Rd), 128, 0, 0)) == nil \|\|`
		1310	`(ctlr->tdba = mallocalign(ctlr->ntd*sizeof(Td), 128, 0, 0)) == nil \|\|`
		1311	`(ctlr->rb = malloc(ctlr->nrdsizeof(Block))) == nil \|\|`
		1312	`(ctlr->tb = malloc(ctlr->ntdsizeof(Block))) == nil)`
		1313	`error(Enomem);`
		1314
		1315	`for(ctlr->nrb = 0; ctlr->nrb < Nrb; ctlr->nrb++){`
		1316	`if((bp = allocb(ctlr->rbsz + BY2PG)) == nil)`
		1317	`error(Enomem);`
		1318	`bp->free = i82563rbfree;`
		1319	`freeb(bp);`
		1320	`}`
		1321	`nrbfull = 0;`
		1322
		1323	`ctlr->edev = edev; /* point back to Ether* */`
		1324	`ctlr->attached = 1;`
		1325	`initmark(&ctlr->wmrb, Nrb, "rcv bufs unprocessed");`
		1326	`initmark(&ctlr->wmrd, Nrd-1, "rcv descrs processed at once");`
		1327	`initmark(&ctlr->wmtd, Ntd-1, "xmit descr queue len");`
		1328
		1329	`snprint(name, sizeof name, "#l%dl", edev->ctlrno);`
		1330	`kproc(name, i82563lproc, edev);`
		1331
		1332	`snprint(name, sizeof name, "#l%dr", edev->ctlrno);`
		1333	`kproc(name, i82563rproc, edev);`
		1334
		1335	`snprint(name, sizeof name, "#l%dt", edev->ctlrno);`
		1336	`kproc(name, i82563tproc, edev);`
		1337
		1338	`i82563txinit(ctlr);`
		1339
		1340	`qunlock(&ctlr->alock);`
		1341	`poperror();`
		1342	`}`
		1343
		1344	`static void`
		1345	`i82563interrupt(Ureg, void arg)`
		1346	`{`
		1347	`Ctlr *ctlr;`
		1348	`Ether *edev;`
		1349	`int icr, im, i;`
		1350
		1351	`edev = arg;`
		1352	`ctlr = edev->ctlr;`
		1353
		1354	`ilock(&ctlr->imlock);`
		1355	`csr32w(ctlr, Imc, ~0);`
		1356	`im = ctlr->im;`
		1357	`i = Nrd; /* don't livelock */`
		1358	`for(icr = csr32r(ctlr, Icr); icr & ctlr->im && i-- > 0;`
		1359	`icr = csr32r(ctlr, Icr)){`
		1360	`if(icr & Lsc){`
		1361	`im &= ~Lsc;`
		1362	`ctlr->lim = icr & Lsc;`
		1363	`wakeup(&ctlr->lrendez);`
		1364	`ctlr->lintr++;`
		1365	`}`
		1366	`if(icr & (Rxt0\|Rxo\|Rxdmt0\|Rxseq\|Ack)){`
		1367	`ctlr->rim = icr & (Rxt0\|Rxo\|Rxdmt0\|Rxseq\|Ack);`
		1368	`im &= ~(Rxt0\|Rxo\|Rxdmt0\|Rxseq\|Ack);`
		1369	`wakeup(&ctlr->rrendez);`
		1370	`ctlr->rintr++;`
		1371	`}`
		1372	`if(icr & Txdw){`
		1373	`im &= ~Txdw;`
		1374	`ctlr->tintr++;`
		1375	`wakeup(&ctlr->trendez);`
		1376	`}`
		1377	`}`
		1378	`ctlr->im = im;`
		1379	`csr32w(ctlr, Ims, im);`
		1380	`iunlock(&ctlr->imlock);`
		1381	`}`
		1382
		1383	`/* assume misrouted interrupts and check all controllers */`
		1384	`static void`
		1385	`i82575interrupt(Ureg, void )`
		1386	`{`
		1387	`Ctlr *ctlr;`
		1388
		1389	`for (ctlr = i82563ctlrhead; ctlr != nil && ctlr->edev != nil;`
		1390	`ctlr = ctlr->next)`
		1391	`i82563interrupt(nil, ctlr->edev);`
		1392	`}`
		1393
		1394	`static int`
		1395	`i82563detach0(Ctlr* ctlr)`
		1396	`{`
		1397	`int r, timeo;`
		1398
		1399	`/*`
		1400	`* Perform a device reset to get the chip back to the`
		1401	`* power-on state, followed by an EEPROM reset to read`
		1402	`* the defaults for some internal registers.`
		1403	`*/`
		1404	`csr32w(ctlr, Imc, ~0);`
		1405	`csr32w(ctlr, Rctl, 0);`
		1406	`csr32w(ctlr, Tctl, 0);`
		1407
		1408	`delay(10);`
		1409
		1410	`r = csr32r(ctlr, Ctrl);`
		1411	`if(ctlr->type == i82566 \|\| ctlr->type == i82567 \|\| ctlr->type == i82579)`
		1412	`r \|= Phyrst;`
		1413	`csr32w(ctlr, Ctrl, Devrst \| r);`
		1414	`delay(1);`
		1415	`for(timeo = 0; timeo < 1000; timeo++){`
		1416	`if(!(csr32r(ctlr, Ctrl) & Devrst))`
		1417	`break;`
		1418	`delay(1);`
		1419	`}`
		1420	`if(csr32r(ctlr, Ctrl) & Devrst)`
		1421	`return -1;`
		1422
		1423	`r = csr32r(ctlr, Ctrlext);`
		1424	`csr32w(ctlr, Ctrlext, r\|Eerst);`
		1425	`delay(1);`
		1426	`for(timeo = 0; timeo < 1000; timeo++){`
		1427	`if(!(csr32r(ctlr, Ctrlext) & Eerst))`
		1428	`break;`
		1429	`delay(1);`
		1430	`}`
		1431	`if(csr32r(ctlr, Ctrlext) & Eerst)`
		1432	`return -1;`
		1433
		1434	`csr32w(ctlr, Imc, ~0);`
		1435	`delay(1);`
		1436	`for(timeo = 0; timeo < 1000; timeo++){`
		1437	`if(!csr32r(ctlr, Icr))`
		1438	`break;`
		1439	`delay(1);`
		1440	`}`
		1441	`if(csr32r(ctlr, Icr))`
		1442	`return -1;`
		1443
		1444	`/*`
		1445	`* Balance Rx/Tx packet buffer.`
		1446	`* No need to set PBA register unless using jumbo, defaults to 32KB`
		1447	`* for receive. If it is changed, then have to do a MAC reset,`
		1448	`* and need to do that at the the right time as it will wipe stuff.`
		1449	`*/`
		1450	`if(ctlr->rbsz > 8192 && (ctlr->type == i82563 \|\| ctlr->type == i82571 \|\|`
		1451	`ctlr->type == i82572)){`
		1452	`ctlr->pba = csr32r(ctlr, Pba);`
		1453	`r = ctlr->pba >> 16;`
		1454	`r += ctlr->pba & 0xffff;`
		1455	`r >>= 1;`
		1456	`csr32w(ctlr, Pba, r);`
		1457	`} else if(ctlr->type == i82573 && ctlr->rbsz > ETHERMAXTU)`
		1458	`csr32w(ctlr, Pba, 14);`
		1459	`ctlr->pba = csr32r(ctlr, Pba);`
		1460
		1461	`r = csr32r(ctlr, Ctrl);`
		1462	`csr32w(ctlr, Ctrl, Slu\|r);`
		1463
		1464	`return 0;`
		1465	`}`
		1466
		1467	`static int`
		1468	`i82563detach(Ctlr* ctlr)`
		1469	`{`
		1470	`int r;`
		1471	`static Lock detlck;`
		1472
		1473	`ilock(&detlck);`
		1474	`r = i82563detach0(ctlr);`
		1475	`iunlock(&detlck);`
		1476	`return r;`
		1477	`}`
		1478
		1479	`static void`
		1480	`i82563shutdown(Ether* ether)`
		1481	`{`
		1482	`i82563detach(ether->ctlr);`
		1483	`}`
		1484
		1485	`static ushort`
		1486	`eeread(Ctlr *ctlr, int adr)`
		1487	`{`
		1488	`ulong n;`
		1489
		1490	`csr32w(ctlr, Eerd, EEstart \| adr << 2);`
		1491	`for (n = 1000000; (csr32r(ctlr, Eerd) & EEdone) == 0 && n-- > 0; )`
		1492	`;`
		1493	`if (n == 0)`
		1494	`panic("i82563: eeread stuck");`
		1495	`return csr32r(ctlr, Eerd) >> 16;`
		1496	`}`
		1497
		1498	`static int`
		1499	`eeload(Ctlr *ctlr)`
		1500	`{`
		1501	`ushort sum;`
		1502	`int data, adr;`
		1503
		1504	`sum = 0;`
		1505	`for (adr = 0; adr < 0x40; adr++) {`
		1506	`data = eeread(ctlr, adr);`
		1507	`ctlr->eeprom[adr] = data;`
		1508	`sum += data;`
		1509	`}`
		1510	`return sum;`
		1511	`}`
		1512
		1513	`static int`
		1514	`fcycle(Ctlr , Flash f)`
		1515	`{`
		1516	`ushort s, i;`
		1517
		1518	`s = f->reg[Fsts];`
		1519	`if((s&Fvalid) == 0)`
		1520	`return -1;`
		1521	`f->reg[Fsts] \|= Fcerr \| Ael;`
		1522	`for(i = 0; i < 10; i++){`
		1523	`if((s&Scip) == 0)`
		1524	`return 0;`
		1525	`delay(1);`
		1526	`s = f->reg[Fsts];`
		1527	`}`
		1528	`return -1;`
		1529	`}`
		1530
		1531	`static int`
		1532	`fread(Ctlr ctlr, Flash f, int ladr)`
		1533	`{`
		1534	`ushort s;`
		1535	`ulong n;`
		1536
		1537	`delay(1);`
		1538	`if(fcycle(ctlr, f) == -1)`
		1539	`return -1;`
		1540	`f->reg[Fsts] \|= Fdone;`
		1541	`f->reg32[Faddr] = ladr;`
		1542
		1543	`/* setup flash control register */`
		1544	`s = f->reg[Fctl];`
		1545	`s &= ~(0x1f << 8);`
		1546	`s \|= (2-1) << 8; /* 2 bytes */`
		1547	`s &= ~(2Flcycle); / read */`
		1548	`f->reg[Fctl] = s \| Fgo;`
		1549
		1550	`for (n = 1000000; (f->reg[Fsts] & Fdone) == 0 && n-- > 0; )`
		1551	`;`
		1552	`if (n == 0)`
		1553	`panic("i82563: fread stuck");`
		1554	`if(f->reg[Fsts] & (Fcerr\|Ael))`
		1555	`return -1;`
		1556	`return f->reg32[Fdata] & 0xffff;`
		1557	`}`
		1558
		1559	`static int`
		1560	`fload(Ctlr *ctlr)`
		1561	`{`
		1562	`ulong data, io, r, adr;`
		1563	`ushort sum;`
		1564	`Flash f;`
		1565
		1566	`io = ctlr->pcidev->mem[1].bar & ~0x0f;`
		1567	`f.reg = vmap(io, ctlr->pcidev->mem[1].size);`
		1568	`if(f.reg == nil)`
		1569	`return -1;`
		1570	`f.reg32 = (void*)f.reg;`
		1571	`f.base = f.reg32[Bfpr] & FMASK(0, 13);`
		1572	`f.lim = (f.reg32[Bfpr]>>16) & FMASK(0, 13);`
		1573	`if(csr32r(ctlr, Eec) & (1<<22))`
		1574	`f.base += (f.lim + 1 - f.base) >> 1;`
		1575	`r = f.base << 12;`
		1576
		1577	`sum = 0;`
		1578	`for (adr = 0; adr < 0x40; adr++) {`
		1579	`data = fread(ctlr, &f, r + adr*2);`
		1580	`if(data == -1)`
		1581	`break;`
		1582	`ctlr->eeprom[adr] = data;`
		1583	`sum += data;`
		1584	`}`
		1585	`vunmap(f.reg, ctlr->pcidev->mem[1].size);`
		1586	`return sum;`
		1587	`}`
		1588
		1589	`static int`
		1590	`i82563reset(Ctlr *ctlr)`
		1591	`{`
		1592	`int i, r;`
		1593
		1594	`if(i82563detach(ctlr))`
		1595	`return -1;`
		1596	`if(ctlr->type == i82566 \|\| ctlr->type == i82567 \|\|`
		1597	`ctlr->type == i82577 \|\| ctlr->type == i82579)`
		1598	`r = fload(ctlr);`
		1599	`else`
		1600	`r = eeload(ctlr);`
		1601	`if (r != 0 && r != 0xBABA){`
		1602	`print("%s: bad EEPROM checksum - %#.4ux\n",`
		1603	`tname[ctlr->type], r);`
		1604	`return -1;`
		1605	`}`
		1606
		1607	`for(i = 0; i < Eaddrlen/2; i++){`
		1608	`ctlr->ra[2*i] = ctlr->eeprom[Ea+i];`
		1609	`ctlr->ra[2*i+1] = ctlr->eeprom[Ea+i] >> 8;`
		1610	`}`
		1611	`r = (csr32r(ctlr, Status) & Lanid) >> 2;`
		1612	`ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */`
		1613
		1614	`r = ctlr->ra[3]<<24 \| ctlr->ra[2]<<16 \| ctlr->ra[1]<<8 \| ctlr->ra[0];`
		1615	`csr32w(ctlr, Ral, r);`
		1616	`r = 0x80000000 \| ctlr->ra[5]<<8 \| ctlr->ra[4];`
		1617	`csr32w(ctlr, Rah, r);`
		1618	`for(i = 1; i < 16; i++){`
		1619	`csr32w(ctlr, Ral+i*8, 0);`
		1620	`csr32w(ctlr, Rah+i*8, 0);`
		1621	`}`
		1622	`memset(ctlr->mta, 0, sizeof(ctlr->mta));`
		1623	`for(i = 0; i < 128; i++)`
		1624	`csr32w(ctlr, Mta + i*4, 0);`
		1625
		1626	`/*`
		1627	`* Does autonegotiation affect this manual setting?`
		1628	`* The correct values here should depend on the PBA value`
		1629	`* and maximum frame length, no?`
		1630	`* ctlr->fcrt[lh] are never set, so default to 0.`
		1631	`*/`
		1632	`csr32w(ctlr, Fcal, 0x00C28001);`
		1633	`csr32w(ctlr, Fcah, 0x0100);`
		1634	`if(ctlr->type != i82579)`
		1635	`csr32w(ctlr, Fct, 0x8808);`
		1636	`csr32w(ctlr, Fcttv, 0x0100);`
		1637
		1638	`ctlr->fcrtl = ctlr->fcrth = 0;`
		1639	`// ctlr->fcrtl = 0x00002000;`
		1640	`// ctlr->fcrth = 0x00004000;`
		1641	`csr32w(ctlr, Fcrtl, ctlr->fcrtl);`
		1642	`csr32w(ctlr, Fcrth, ctlr->fcrth);`
		1643
		1644	`return 0;`
		1645	`}`
		1646
		1647	`static void`
		1648	`i82563pci(void)`
		1649	`{`
		1650	`int type;`
		1651	`ulong io;`
		1652	`void *mem;`
		1653	`Pcidev *p;`
		1654	`Ctlr *ctlr;`
		1655
		1656	`p = nil;`
		1657	`while(p = pcimatch(p, 0x8086, 0)){`
		1658	`switch(p->did){`
		1659	`default:`
		1660	`continue;`
		1661	`case 0x1096:`
		1662	`case 0x10ba:`
		1663	`type = i82563;`
		1664	`break;`
		1665	`case 0x1049: /* mm */`
		1666	`case 0x104a: /* dm */`
		1667	`case 0x104b: /* dc */`
		1668	`case 0x104d: /* mc */`
		1669	`case 0x10bd: /* dm */`
		1670	`case 0x294c: /* dc-2 */`
		1671	`type = i82566;`
		1672	`break;`
		1673	`case 0x10cd: /* lf */`
		1674	`case 0x10ce: /* v-2 */`
		1675	`case 0x10de: /* lm-3 */`
		1676	`case 0x10f5: /* lm-2 */`
		1677	`type = i82567;`
		1678	`break;`
		1679	`case 0x10a4:`
		1680	`case 0x105e:`
		1681	`type = i82571;`
		1682	`break;`
		1683	`case 0x107d: /* eb copper */`
		1684	`case 0x107e: /* ei fiber */`
		1685	`case 0x107f: /* ei */`
		1686	`case 0x10b9: /* sic, 82572gi */`
		1687	`type = i82572;`
		1688	`break;`
		1689	`case 0x108b: /* v */`
		1690	`case 0x108c: /* e (iamt) */`
		1691	`case 0x109a: /* l */`
		1692	`type = i82573;`
		1693	`break;`
		1694	`case 0x10d3: /* l */`
		1695	`type = i82574;`
		1696	`break;`
		1697	`case 0x10a7: /* 82575eb: one of a pair of controllers */`
		1698	`type = i82575;`
		1699	`break;`
		1700	`case 0x10c9: /* 82576 copper */`
		1701	`case 0x10e6: /* 82576 fiber */`
		1702	`case 0x10e7: /* 82576 serdes */`
		1703	`type = i82576;`
		1704	`break;`
		1705	`case 0x10ea: /* 82577lm */`
		1706	`type = i82577;`
		1707	`break;`
		1708	`case 0x1502: /* 82579lm */`
		1709	`case 0x1503: /* 82579v */`
		1710	`type = i82579;`
		1711	`break;`
		1712	`}`
		1713
		1714	`io = p->mem[0].bar & ~0x0F;`
		1715	`mem = vmap(io, p->mem[0].size);`
		1716	`if(mem == nil){`
		1717	`print("%s: can't map %.8lux\n", tname[type], io);`
		1718	`continue;`
		1719	`}`
		1720	`ctlr = malloc(sizeof(Ctlr));`
		1721	`if(ctlr == nil) {`
		1722	`vunmap(mem, p->mem[0].size);`
		1723	`error(Enomem);`
		1724	`}`
		1725	`ctlr->port = io;`
		1726	`ctlr->pcidev = p;`
		1727	`ctlr->type = type;`
		1728	`/*`
		1729	`* on the assumption that allowing jumbo packets makes`
		1730	`* the controller much slower (as is true of the 82579),`
		1731	`* never allow jumbos.`
		1732	`*/`
		1733	`// ctlr->rbsz = rbtab[type];`
		1734	`ctlr->rbsz = ETHERMAXTU;`
		1735	`ctlr->nic = mem;`
		1736
		1737	`if(i82563reset(ctlr)){`
		1738	`vunmap(mem, p->mem[0].size);`
		1739	`free(ctlr);`
		1740	`continue;`
		1741	`}`
		1742	`pcisetbme(p);`
		1743
		1744	`if(i82563ctlrhead != nil)`
		1745	`i82563ctlrtail->next = ctlr;`
		1746	`else`
		1747	`i82563ctlrhead = ctlr;`
		1748	`i82563ctlrtail = ctlr;`
		1749	`}`
		1750	`}`
		1751
		1752	`static int`
		1753	`pnp(Ether* edev, int type)`
		1754	`{`
		1755	`Ctlr *ctlr;`
		1756	`static int done;`
		1757
		1758	`if(!done) {`
		1759	`i82563pci();`
		1760	`done = 1;`
		1761	`}`
		1762
		1763	`/*`
		1764	`* Any adapter matches if no edev->port is supplied,`
		1765	`* otherwise the ports must match.`
		1766	`*/`
		1767	`for(ctlr = i82563ctlrhead; ctlr != nil; ctlr = ctlr->next){`
		1768	`if(ctlr->active)`
		1769	`continue;`
		1770	`if(type != Iany && ctlr->type != type)`
		1771	`continue;`
		1772	`if(edev->port == 0 \|\| edev->port == ctlr->port){`
		1773	`ctlr->active = 1;`
		1774	`break;`
		1775	`}`
		1776	`}`
		1777	`if(ctlr == nil)`
		1778	`return -1;`
		1779
		1780	`edev->ctlr = ctlr;`
		1781	`ctlr->edev = edev; /* point back to Ether* */`
		1782	`edev->port = ctlr->port;`
		1783	`edev->irq = ctlr->pcidev->intl;`
		1784	`edev->tbdf = ctlr->pcidev->tbdf;`
		1785	`edev->mbps = 1000;`
		1786	`edev->maxmtu = ctlr->rbsz;`
		1787	`memmove(edev->ea, ctlr->ra, Eaddrlen);`
		1788
		1789	`/*`
		1790	`* Linkage to the generic ethernet driver.`
		1791	`*/`
		1792	`edev->attach = i82563attach;`
		1793	`edev->transmit = i82563transmit;`
		1794	`edev->interrupt = (ctlr->type == i82575?`
		1795	`i82575interrupt: i82563interrupt);`
		1796	`edev->ifstat = i82563ifstat;`
		1797	`edev->ctl = i82563ctl;`
		1798
		1799	`edev->arg = edev;`
		1800	`edev->promiscuous = i82563promiscuous;`
		1801	`edev->shutdown = i82563shutdown;`
		1802	`edev->multicast = i82563multicast;`
		1803
		1804	`return 0;`
		1805	`}`
		1806
		1807	`static int`
		1808	`anypnp(Ether *e)`
		1809	`{`
		1810	`return pnp(e, Iany);`
		1811	`}`
		1812
		1813	`static int`
		1814	`i82563pnp(Ether *e)`
		1815	`{`
		1816	`return pnp(e, i82563);`
		1817	`}`
		1818
		1819	`static int`
		1820	`i82566pnp(Ether *e)`
		1821	`{`
		1822	`return pnp(e, i82566);`
		1823	`}`
		1824
		1825	`static int`
		1826	`i82571pnp(Ether *e)`
		1827	`{`
		1828	`return pnp(e, i82571);`
		1829	`}`
		1830
		1831	`static int`
		1832	`i82572pnp(Ether *e)`
		1833	`{`
		1834	`return pnp(e, i82572);`
		1835	`}`
		1836
		1837	`static int`
		1838	`i82573pnp(Ether *e)`
		1839	`{`
		1840	`return pnp(e, i82573);`
		1841	`}`
		1842
		1843	`static int`
		1844	`i82575pnp(Ether *e)`
		1845	`{`
		1846	`return pnp(e, i82575);`
		1847	`}`
		1848
		1849	`static int`
		1850	`i82579pnp(Ether *e)`
		1851	`{`
		1852	`return pnp(e, i82579);`
		1853	`}`
		1854
		1855	`void`
		1856	`ether82563link(void)`
		1857	`{`
		1858	`/* recognise lots of model numbers for debugging assistance */`
		1859	`addethercard("i82563", i82563pnp);`
		1860	`addethercard("i82566", i82566pnp);`
		1861	`addethercard("i82571", i82571pnp);`
		1862	`addethercard("i82572", i82572pnp);`
		1863	`addethercard("i82573", i82573pnp);`
		1864	`addethercard("i82575", i82575pnp);`
		1865	`addethercard("i82579", i82579pnp);`
		1866	`addethercard("igbepcie", anypnp);`
		1867	`}`

Subversion Repositories planix.SVN

(root)/os/branches/planix-v0/sys/src/9/pc/ether82563.c – Rev 9