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#include "mem.h"
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#define KB 1024
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#define MB (1024*1024)
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/*
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* Some machine instructions not handled by 8[al].
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*/
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#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
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#define FARJUMP(s, o) BYTE $0xEA; /* far jump to ptr32:16 */\
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LONG $o; WORD $s
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#define NOP BYTE $0x90
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#define HLT BYTE $0xF4
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/*
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* Macro for calculating offset within the page directory base.
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* Note that this is assembler-specific hence the '<<2'.
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*/
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#define PDO(a) (((((a))>>22) & 0x03FF)<<2)
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/*
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* May enter here either from the 16-bit real-mode startup or
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* from other 32-bit protected mode code. For the latter case must
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* make sure the GDT is set as it would be by the 16-bit code:
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* disable interrupts;
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* load the GDT with the table in _gdt32p;
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* load all the data segments
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* load the code segment via a far jump.
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*/
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TEXT _start32p(SB), $0
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/* if distance to _start32p32 changes, update the offset after 0xEB. */
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// jmp .+32 (_start32p32).
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BYTE $0xEB; BYTE $(2+3*2*4+2+4)
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NOP; NOP
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TEXT _gdt32p(SB), $0
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LONG $0x0000; LONG $0
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LONG $0xFFFF; LONG $(SEGG|SEGB|(0xF<<16)|SEGP|SEGPL(0)|SEGDATA|SEGW)
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LONG $0xFFFF; LONG $(SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(0)|SEGEXEC|SEGR)
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TEXT _gdtptr32p(SB), $0
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WORD $(3*8)
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LONG $_gdt32p-KZERO(SB)
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_start32p32:
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CLI
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MOVL AX, _multibootheader+(48-KZERO)(SB)
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MOVL BX, _multibootheader+(52-KZERO)(SB)
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MOVL $_gdtptr32p-KZERO(SB), AX
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MOVL (AX), GDTR
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MOVL $KDSEL, AX
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MOVW AX, DS
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MOVW AX, ES
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MOVW AX, FS
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MOVW AX, GS
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MOVW AX, SS
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DELAY
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FARJUMP(KESEL, _start32pg-KZERO(SB))
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/*
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* Make the basic page tables for processor 0. Eight pages are needed for
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* the basic set:
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* a page directory, 5 pages pf page tables for mapping the first 20MB of
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* physical memory, a single physical and virtual page for the Mach structure,
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* and a page to be used later for the GDT.
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*
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* The remaining PTEs will be allocated later when memory is sized.
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* Could clear BSS here too when clearing the space for the tables,
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* but that would violate the separation of church and state.
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* The first aligned page after end[] was used for passing BIOS parameters
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* by the real-mode startup, now it's BIOSTABLES.
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*/
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TEXT _start32pg(SB), $0 /* CHECK alignment (16) */
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DELAY
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MOVL $end-KZERO(SB), DX /* clear pages for the tables etc. */
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/* start must be page aligned, skip boot params page */
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ADDL $(2*BY2PG-1), DX
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ANDL $~(BY2PG-1), DX
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/*
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* zero mach page & gdt in low memory
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*/
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MOVL $(CPU0MACH-KZERO), DI
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XORL AX, AX
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MOVL $(2*BY2PG), CX /* mach (phys & virt) & gdt */
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SHRL $2, CX
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CLD
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REP; STOSL /* zero mach & gdt pages */
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/*
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* zero pdb and pte for low memory
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*/
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MOVL DX, DI /* first page after end & boot params */
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XORL AX, AX
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MOVL $((1+LOWPTEPAGES)*BY2PG), CX /* pdb, n pte */
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SHRL $2, CX
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CLD
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REP; STOSL /* zero pdb & pte pages */
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/*
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* populate pdb for low memory (20MB)
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*/
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MOVL DX, AX /* bootstrap processor PDB (page 0) */
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MOVL DX, DI /* save it for later */
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MOVL $(PTEWRITE|PTEVALID), BX/* page permissions */
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ADDL $BY2PG, DX /* -> PA of first page of page table (page 1) */
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ADDL $PDO(KZERO), AX /* page directory offset for KZERO */
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MOVL DX, (AX) /* PTE's for KZERO */
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ORL BX, (AX)
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/* should be LOWPTEPAGES-1 repetitions of this fragment */
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ADDL $BY2PG, DX /* -> PA of second page of page table (page 2) */
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ADDL $4, AX /* page dir. offset for KZERO+4MB */
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MOVL DX, (AX) /* PTE's for KZERO */
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ORL BX, (AX)
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ADDL $BY2PG, DX /* -> PA of third page of page table (page 3) */
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ADDL $4, AX /* page dir. offset for KZERO+8MB */
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MOVL DX, (AX) /* PTE's for KZERO */
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ORL BX, (AX)
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ADDL $BY2PG, DX /* -> PA of fourth page of page table (page 4) */
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ADDL $4, AX /* page dir. offset for KZERO+12MB */
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MOVL DX, (AX) /* PTE's for KZERO */
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ORL BX, (AX)
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ADDL $BY2PG, DX /* -> PA of fifth page of page table (page 5) */
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ADDL $4, AX /* page dir. offset for KZERO+16MB */
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MOVL DX, (AX) /* PTE's for KZERO */
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ORL BX, (AX)
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/*
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* populate page tables for low memory
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*/
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MOVL DI, AX
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ADDL $BY2PG, AX /* PA of first page of page table */
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MOVL $(MemMin/BY2PG), CX
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_setpte:
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MOVL BX, (AX)
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ADDL $(1<<PGSHIFT), BX
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ADDL $4, AX
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LOOP _setpte
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/*
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* map the Mach page
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*/
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MOVL DI, AX
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ADDL $BY2PG, AX /* PA of first page of page table */
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MOVL $(CPU0MACH-KZERO), DX /* -> PA of Mach structure */
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MOVL $CPU0MACH, BX /* VA of Mach structure */
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SHRL $10, BX /* create offset into PTEs */
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ANDL $(0x3FF<<2), BX
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ADDL BX, AX /* PTE offset for Mach structure */
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MOVL DX, (AX) /* create PTE for Mach */
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MOVL $(PTEWRITE|PTEVALID), BX/* page permissions */
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ORL BX, (AX)
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/*
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* Now ready to use the new map. Initialise CR0 (assume the BIOS gets
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* it mostly correct for this processor type w.r.t. caches and FPU).
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* It is necessary on some processors to follow mode switching
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* with a JMP instruction to clear the prefetch queues.
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* The instruction to switch modes and the following jump instruction
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* should be identity-mapped; to this end double map KZERO at
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* virtual 0 and undo the mapping once virtual nirvana has been attained.
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* If paging is already on, don't load CR3 before setting CR0, in which
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* case most of this is a NOP and the 2nd load of CR3 actually does
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* the business.
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*/
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MOVL DI, CX /* load address of PDB */
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/* double-map first 20 MB, since we are running at 7 or 9 MB */
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/* should be LOWPTEPAGES repetitions */
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MOVL PDO(KZERO)(CX), DX /* double-map KZERO at 0 */
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MOVL DX, PDO(0)(CX)
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MOVL PDO(KZERO+4*MB)(CX), DX
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MOVL DX, PDO(4*MB)(CX)
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MOVL PDO(KZERO+8*MB)(CX), DX
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MOVL DX, PDO(8*MB)(CX)
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MOVL PDO(KZERO+12*MB)(CX), DX
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MOVL DX, PDO(12*MB)(CX)
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MOVL PDO(KZERO+16*MB)(CX), DX
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MOVL DX, PDO(16*MB)(CX)
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MOVL CR0, DX
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MOVL DX, AX
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ANDL $PG, AX /* check paging not already on */
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JNE _nocr3load
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MOVL CX, CR3 /* paging off, safe to load cr3 */
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_nocr3load:
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ORL $(PG|0x10000), DX /* PG|WP */
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ANDL $~0x6000000A, DX /* ~(CD|NW|TS|MP) */
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MOVL $_startpg(SB), AX
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TESTL $KZERO, AX /* want to run protected or virtual? */
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JEQ _to32v /* protected */
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MOVL DX, CR0 /* turn on paging */
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JMP* AX /* headfirst into the new world */
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TEXT _startpg(SB), $0
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// MOVL $0, PDO(0)(CX) /* undo double-map of KZERO at 0 */
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MOVL CX, CR3 /* load and flush the mmu */
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_to32v:
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MOVL $_start32v(SB), AX
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JMP* AX /* into the dorkness */
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