| 2 |
- |
1 |
enum {
|
|
|
2 |
Mhz = 1000*1000,
|
|
|
3 |
};
|
|
|
4 |
|
|
|
5 |
/*
|
|
|
6 |
* duarts, frequency and registers
|
|
|
7 |
*/
|
|
|
8 |
#define DUARTFREQ 3672000
|
|
|
9 |
|
|
|
10 |
/*
|
|
|
11 |
* interrupt levels on CPU boards.
|
|
|
12 |
*/
|
|
|
13 |
enum
|
|
|
14 |
{
|
|
|
15 |
ILmin = 2,
|
|
|
16 |
ILpci = 2,
|
|
|
17 |
ILehci = 3,
|
|
|
18 |
ILenet1 = 4, /* arge1 @ 0x19:: w switch */
|
|
|
19 |
ILenet0 = 5, /* arge0 @ 0x1a:: */
|
|
|
20 |
ILduart0 = 6, /* actually APB, uart is subintr 3 */
|
|
|
21 |
ILclock = 7,
|
|
|
22 |
ILmax = 7,
|
|
|
23 |
|
|
|
24 |
ILshift = 8,
|
|
|
25 |
};
|
|
|
26 |
|
|
|
27 |
#define Rstblockbase (ulong *)KSEG1ADDR(0x18060000)
|
|
|
28 |
|
|
|
29 |
#define Rstwdogctl (ulong *)KSEG1ADDR(0x18060008)
|
|
|
30 |
#define Wdoglast (1 << 31)
|
|
|
31 |
#define Wdogmask 3
|
|
|
32 |
#define Wdognoaction 0
|
|
|
33 |
#define Wdoggpintr 1
|
|
|
34 |
#define Wdognmi 2
|
|
|
35 |
#define Wdogreset 3
|
|
|
36 |
#define Rstwdogtimer (ulong *)KSEG1ADDR(0x1806000c)
|
|
|
37 |
|
|
|
38 |
/*
|
|
|
39 |
* APB interrupt status and mask register and interrupt bits
|
|
|
40 |
*/
|
|
|
41 |
#define Apbintrsts (ulong *)KSEG1ADDR(0x18060010)
|
|
|
42 |
#define Apbintrmask (ulong *)KSEG1ADDR(0x18060014)
|
|
|
43 |
#define Apbintrtimer 0
|
|
|
44 |
#define Apbintrerror 1
|
|
|
45 |
#define Apbintrgpio 2
|
|
|
46 |
#define Apbintruart 3
|
|
|
47 |
#define Apbintrwatchdog 4
|
|
|
48 |
#define Apbintrperf 5
|
|
|
49 |
#define Apbintrohci 6
|
|
|
50 |
#define Apbintrdma 7
|
|
|
51 |
|
|
|
52 |
#define Pciintrsts (ulong *)KSEG1ADDR(0x18060018)
|
|
|
53 |
#define Pciintrmask (ulong *)KSEG1ADDR(0x1806001C)
|
|
|
54 |
#define PCI_INTR_CORE (1 << 4)
|
|
|
55 |
|
|
|
56 |
#define Reset (ulong *)KSEG1ADDR(0x18060024)
|
|
|
57 |
#define Rstfullchip (1 << 24) /* same as pulling the reset pin */
|
|
|
58 |
#define Rstcpucold (1 << 20) /* cold reset */
|
|
|
59 |
#define Rstge1mac (1 << 13)
|
|
|
60 |
#define Rstge1phy (1 << 12)
|
|
|
61 |
#define Rstge0mac (1 << 9)
|
|
|
62 |
#define Rstge0phy (1 << 8)
|
|
|
63 |
#define Rstusbohcidll (1 << 6)
|
|
|
64 |
#define Rstusbhost (1 << 5)
|
|
|
65 |
#define Rstusbphy (1 << 4)
|
|
|
66 |
#define Rstpcibus (1 << 1)
|
|
|
67 |
#define Rstpcicore (1 << 0)
|
|
|
68 |
|
|
|
69 |
/*
|
|
|
70 |
* mostly PCI from here on
|
|
|
71 |
*/
|
|
|
72 |
|
|
|
73 |
typedef struct Pcisiz Pcisiz;
|
|
|
74 |
typedef struct Pcidev Pcidev;
|
|
|
75 |
typedef struct Vctl Vctl;
|
|
|
76 |
|
|
|
77 |
struct Vctl {
|
|
|
78 |
Vctl* next; /* handlers on this vector */
|
|
|
79 |
|
|
|
80 |
char name[KNAMELEN]; /* of driver */
|
|
|
81 |
int isintr; /* interrupt or fault/trap */
|
|
|
82 |
int irq;
|
|
|
83 |
int tbdf;
|
|
|
84 |
int (*isr)(int); /* get isr bit for this irq */
|
|
|
85 |
int (*eoi)(int); /* eoi */
|
|
|
86 |
|
|
|
87 |
void (*f)(Ureg*, void*); /* handler to call */
|
|
|
88 |
void* a; /* argument to call it with */
|
|
|
89 |
};
|
|
|
90 |
|
|
|
91 |
enum {
|
|
|
92 |
BusCBUS = 0, /* Corollary CBUS */
|
|
|
93 |
BusCBUSII, /* Corollary CBUS II */
|
|
|
94 |
BusEISA, /* Extended ISA */
|
|
|
95 |
BusFUTURE, /* IEEE Futurebus */
|
|
|
96 |
BusINTERN, /* Internal bus */
|
|
|
97 |
BusISA, /* Industry Standard Architecture */
|
|
|
98 |
BusMBI, /* Multibus I */
|
|
|
99 |
BusMBII, /* Multibus II */
|
|
|
100 |
BusMCA, /* Micro Channel Architecture */
|
|
|
101 |
BusMPI, /* MPI */
|
|
|
102 |
BusMPSA, /* MPSA */
|
|
|
103 |
BusNUBUS, /* Apple Macintosh NuBus */
|
|
|
104 |
BusPCI, /* Peripheral Component Interconnect */
|
|
|
105 |
BusPCMCIA, /* PC Memory Card International Association */
|
|
|
106 |
BusTC, /* DEC TurboChannel */
|
|
|
107 |
BusVL, /* VESA Local bus */
|
|
|
108 |
BusVME, /* VMEbus */
|
|
|
109 |
BusXPRESS, /* Express System Bus */
|
|
|
110 |
};
|
|
|
111 |
|
|
|
112 |
#define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
|
|
|
113 |
#define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
|
|
|
114 |
#define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
|
|
|
115 |
#define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
|
|
|
116 |
#define BUSTYPE(tbdf) ((tbdf)>>24)
|
|
|
117 |
#define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
|
|
|
118 |
#define BUSUNKNOWN (-1)
|
|
|
119 |
|
|
|
120 |
enum {
|
|
|
121 |
MaxEISA = 16,
|
|
|
122 |
CfgEISA = 0xC80,
|
|
|
123 |
};
|
|
|
124 |
|
|
|
125 |
/*
|
|
|
126 |
* PCI support code.
|
|
|
127 |
*/
|
|
|
128 |
enum { /* type 0 & type 1 pre-defined header */
|
|
|
129 |
PciVID = 0x00, /* vendor ID */
|
|
|
130 |
PciDID = 0x02, /* device ID */
|
|
|
131 |
PciPCR = 0x04, /* command */
|
|
|
132 |
PciPSR = 0x06, /* status */
|
|
|
133 |
PciRID = 0x08, /* revision ID */
|
|
|
134 |
PciCCRp = 0x09, /* programming interface class code */
|
|
|
135 |
PciCCRu = 0x0A, /* sub-class code */
|
|
|
136 |
PciCCRb = 0x0B, /* base class code */
|
|
|
137 |
PciCLS = 0x0C, /* cache line size */
|
|
|
138 |
PciLTR = 0x0D, /* latency timer */
|
|
|
139 |
PciHDT = 0x0E, /* header type */
|
|
|
140 |
PciBST = 0x0F, /* BIST */
|
|
|
141 |
|
|
|
142 |
PciBAR0 = 0x10, /* base address */
|
|
|
143 |
PciBAR1 = 0x14,
|
|
|
144 |
|
|
|
145 |
PciINTL = 0x3C, /* interrupt line */
|
|
|
146 |
PciINTP = 0x3D, /* interrupt pin */
|
|
|
147 |
};
|
|
|
148 |
|
|
|
149 |
/* ccrb (base class code) values; controller types */
|
|
|
150 |
enum {
|
|
|
151 |
Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
|
|
|
152 |
Pcibcstore = 1, /* mass storage */
|
|
|
153 |
Pcibcnet = 2, /* network */
|
|
|
154 |
Pcibcdisp = 3, /* display */
|
|
|
155 |
Pcibcmmedia = 4, /* multimedia */
|
|
|
156 |
Pcibcmem = 5, /* memory */
|
|
|
157 |
Pcibcbridge = 6, /* bridge */
|
|
|
158 |
Pcibccomm = 7, /* simple comms (e.g., serial) */
|
|
|
159 |
Pcibcbasesys = 8, /* base system */
|
|
|
160 |
Pcibcinput = 9, /* input */
|
|
|
161 |
Pcibcdock = 0xa, /* docking stations */
|
|
|
162 |
Pcibcproc = 0xb, /* processors */
|
|
|
163 |
Pcibcserial = 0xc, /* serial bus (e.g., USB) */
|
|
|
164 |
Pcibcwireless = 0xd, /* wireless */
|
|
|
165 |
Pcibcintell = 0xe, /* intelligent i/o */
|
|
|
166 |
Pcibcsatcom = 0xf, /* satellite comms */
|
|
|
167 |
Pcibccrypto = 0x10, /* encryption/decryption */
|
|
|
168 |
Pcibcdacq = 0x11, /* data acquisition & signal proc. */
|
|
|
169 |
};
|
|
|
170 |
|
|
|
171 |
/* ccru (sub-class code) values; common cases only */
|
|
|
172 |
enum {
|
|
|
173 |
/* mass storage */
|
|
|
174 |
Pciscscsi = 0, /* SCSI */
|
|
|
175 |
Pciscide = 1, /* IDE (ATA) */
|
|
|
176 |
Pciscsata = 6, /* SATA */
|
|
|
177 |
|
|
|
178 |
/* network */
|
|
|
179 |
Pciscether = 0, /* Ethernet */
|
|
|
180 |
|
|
|
181 |
/* display */
|
|
|
182 |
Pciscvga = 0, /* VGA */
|
|
|
183 |
Pciscxga = 1, /* XGA */
|
|
|
184 |
Pcisc3d = 2, /* 3D */
|
|
|
185 |
|
|
|
186 |
/* bridges */
|
|
|
187 |
Pcischostpci = 0, /* host/pci */
|
|
|
188 |
Pciscpcicpci = 1, /* pci/pci */
|
|
|
189 |
|
|
|
190 |
/* simple comms */
|
|
|
191 |
Pciscserial = 0, /* 16450, etc. */
|
|
|
192 |
Pciscmultiser = 1, /* multiport serial */
|
|
|
193 |
|
|
|
194 |
/* serial bus */
|
|
|
195 |
Pciscusb = 3, /* USB */
|
|
|
196 |
};
|
|
|
197 |
|
|
|
198 |
enum { /* type 0 pre-defined header */
|
|
|
199 |
PciCIS = 0x28, /* cardbus CIS pointer */
|
|
|
200 |
PciSVID = 0x2C, /* subsystem vendor ID */
|
|
|
201 |
PciSID = 0x2E, /* cardbus CIS pointer */
|
|
|
202 |
PciEBAR0 = 0x30, /* expansion ROM base address */
|
|
|
203 |
PciMGNT = 0x3E, /* burst period length */
|
|
|
204 |
PciMLT = 0x3F, /* maximum latency between bursts */
|
|
|
205 |
};
|
|
|
206 |
|
|
|
207 |
enum { /* type 1 pre-defined header */
|
|
|
208 |
PciPBN = 0x18, /* primary bus number */
|
|
|
209 |
PciSBN = 0x19, /* secondary bus number */
|
|
|
210 |
PciUBN = 0x1A, /* subordinate bus number */
|
|
|
211 |
PciSLTR = 0x1B, /* secondary latency timer */
|
|
|
212 |
PciIBR = 0x1C, /* I/O base */
|
|
|
213 |
PciILR = 0x1D, /* I/O limit */
|
|
|
214 |
PciSPSR = 0x1E, /* secondary status */
|
|
|
215 |
PciMBR = 0x20, /* memory base */
|
|
|
216 |
PciMLR = 0x22, /* memory limit */
|
|
|
217 |
PciPMBR = 0x24, /* prefetchable memory base */
|
|
|
218 |
PciPMLR = 0x26, /* prefetchable memory limit */
|
|
|
219 |
PciPUBR = 0x28, /* prefetchable base upper 32 bits */
|
|
|
220 |
PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
|
|
|
221 |
PciIUBR = 0x30, /* I/O base upper 16 bits */
|
|
|
222 |
PciIULR = 0x32, /* I/O limit upper 16 bits */
|
|
|
223 |
PciEBAR1 = 0x28, /* expansion ROM base address */
|
|
|
224 |
PciBCR = 0x3E, /* bridge control register */
|
|
|
225 |
};
|
|
|
226 |
|
|
|
227 |
enum { /* type 2 pre-defined header */
|
|
|
228 |
PciCBExCA = 0x10,
|
|
|
229 |
PciCBSPSR = 0x16,
|
|
|
230 |
PciCBPBN = 0x18, /* primary bus number */
|
|
|
231 |
PciCBSBN = 0x19, /* secondary bus number */
|
|
|
232 |
PciCBUBN = 0x1A, /* subordinate bus number */
|
|
|
233 |
PciCBSLTR = 0x1B, /* secondary latency timer */
|
|
|
234 |
PciCBMBR0 = 0x1C,
|
|
|
235 |
PciCBMLR0 = 0x20,
|
|
|
236 |
PciCBMBR1 = 0x24,
|
|
|
237 |
PciCBMLR1 = 0x28,
|
|
|
238 |
PciCBIBR0 = 0x2C, /* I/O base */
|
|
|
239 |
PciCBILR0 = 0x30, /* I/O limit */
|
|
|
240 |
PciCBIBR1 = 0x34, /* I/O base */
|
|
|
241 |
PciCBILR1 = 0x38, /* I/O limit */
|
|
|
242 |
PciCBSVID = 0x40, /* subsystem vendor ID */
|
|
|
243 |
PciCBSID = 0x42, /* subsystem ID */
|
|
|
244 |
PciCBLMBAR = 0x44, /* legacy mode base address */
|
|
|
245 |
};
|
|
|
246 |
|
|
|
247 |
struct Pcisiz
|
|
|
248 |
{
|
|
|
249 |
Pcidev* dev;
|
|
|
250 |
int siz;
|
|
|
251 |
int bar;
|
|
|
252 |
};
|
|
|
253 |
|
|
|
254 |
struct Pcidev
|
|
|
255 |
{
|
|
|
256 |
int tbdf; /* type+bus+device+function */
|
|
|
257 |
ushort vid; /* vendor ID */
|
|
|
258 |
ushort did; /* device ID */
|
|
|
259 |
|
|
|
260 |
ushort pcr;
|
|
|
261 |
|
|
|
262 |
uchar rid;
|
|
|
263 |
uchar ccrp;
|
|
|
264 |
uchar ccru;
|
|
|
265 |
uchar ccrb;
|
|
|
266 |
uchar cls;
|
|
|
267 |
uchar ltr;
|
|
|
268 |
|
|
|
269 |
struct {
|
|
|
270 |
ulong bar; /* base address */
|
|
|
271 |
int size;
|
|
|
272 |
} mem[6];
|
|
|
273 |
|
|
|
274 |
struct {
|
|
|
275 |
ulong bar;
|
|
|
276 |
int size;
|
|
|
277 |
} rom;
|
|
|
278 |
uchar intl; /* interrupt line */
|
|
|
279 |
|
|
|
280 |
Pcidev* list;
|
|
|
281 |
Pcidev* link; /* next device on this bno */
|
|
|
282 |
|
|
|
283 |
Pcidev* bridge; /* down a bus */
|
|
|
284 |
struct {
|
|
|
285 |
ulong bar;
|
|
|
286 |
int size;
|
|
|
287 |
} ioa, mema;
|
|
|
288 |
|
|
|
289 |
int pmrb; /* power management register block */
|
|
|
290 |
};
|
|
|
291 |
|
|
|
292 |
enum {
|
|
|
293 |
/* vendor ids */
|
|
|
294 |
Vatiamd = 0x1002,
|
|
|
295 |
Vintel = 0x8086,
|
|
|
296 |
Vjmicron= 0x197b,
|
|
|
297 |
Vmarvell= 0x1b4b,
|
|
|
298 |
Vmyricom= 0x14c1,
|
|
|
299 |
};
|
|
|
300 |
|
|
|
301 |
#define PCIWINDOW 0
|
|
|
302 |
#define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
|
|
|
303 |
#define ISAWINDOW 0
|
|
|
304 |
#define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
|
|
|
305 |
|
|
|
306 |
/* SMBus transactions */
|
|
|
307 |
enum
|
|
|
308 |
{
|
|
|
309 |
SMBquick, /* sends address only */
|
|
|
310 |
|
|
|
311 |
/* write */
|
|
|
312 |
SMBsend, /* sends address and cmd */
|
|
|
313 |
SMBbytewrite, /* sends address and cmd and 1 byte */
|
|
|
314 |
SMBwordwrite, /* sends address and cmd and 2 bytes */
|
|
|
315 |
|
|
|
316 |
/* read */
|
|
|
317 |
SMBrecv, /* sends address, recvs 1 byte */
|
|
|
318 |
SMBbyteread, /* sends address and cmd, recv's byte */
|
|
|
319 |
SMBwordread, /* sends address and cmd, recv's 2 bytes */
|
|
|
320 |
};
|
|
|
321 |
|
|
|
322 |
typedef struct SMBus SMBus;
|
|
|
323 |
struct SMBus {
|
|
|
324 |
QLock; /* mutex */
|
|
|
325 |
Rendez r; /* rendezvous point for completion interrupts */
|
|
|
326 |
void *arg; /* implementation dependent */
|
|
|
327 |
ulong base; /* port or memory base of smbus */
|
|
|
328 |
int busy;
|
|
|
329 |
void (*transact)(SMBus*, int, int, int, uchar*);
|
|
|
330 |
};
|
|
|
331 |
|
|
|
332 |
#pragma varargck type "T" int
|
|
|
333 |
#pragma varargck type "T" uint
|