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see ยง5.4.40 (p.142) pllx_* (2 regs)
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out of u-boot, these are the settings:
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---
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pllx	base 0x4003e80c:
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		enabled, no locked
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		divp == 0 (post divider == 2^0 == 1)
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		divn == 1000 (feedback divider)
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		divm == 12 (input divider)
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	misc 0x100: pllx_cpcon == 1		[ should be 12 ]
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super cclk divider 0x80000000:
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	enabled
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	dividend == 0 (thus 1)
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	divisor == 0 (thus 1)
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super sclk divider 0x0:
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	disabled
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	dividend == 0 (thus 1)
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	divisor == 0 (thus 1)
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---