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/*
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 *	mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
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 *
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 *	p -= b*m
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 *
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 *	each step looks like:
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 *		hi,lo = m*b[i]
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 *		lo += oldhi + carry
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 *		hi += carry
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 *		p[i] += lo
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 *		oldhi = hi
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 *
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 *	the registers are:
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 *		b = R1
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 *		n = R4
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 *		m = R5
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 *		p = R6
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 *		i = R7
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 *		hi = R8		- constrained by hardware
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 *		lo = R9		- constrained by hardware
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 *		oldhi = R10
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 *		tmp = R11
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 *
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 */
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TEXT	mpvecdigmulsub(SB),$0
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	MOVW	n+4(FP),R4
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	MOVW	m+8(FP),R5
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	MOVW	p+12(FP),R6
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	MOVW	R0, R10		/* oldhi = 0 */
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_mulsubloop:
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	MOVW	0(R1), R9	/* lo = b[i] */
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	ADDU	$4, R1
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	MOVW	0(R6), R11	/* tmp = p[i] */
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	MULU	R9, R5
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	MOVW	HI, R8		/* hi = (b[i] * m)>>32 */
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	MOVW	LO, R9		/* lo = b[i] * m */
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	ADDU	R10, R9		/* lo += oldhi */
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	SGTU	R10, R9, R2
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	ADDU	R2, R8		/* hi += carry */
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	SUBU	R9, R11, R3	/* tmp -= lo */
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	SGTU	R3, R11, R2
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	ADDU	R2, R8		/* hi += carry */
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	MOVW	R3, 0(R6)	/* p[i] = tmp */
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	ADDU	$4, R6
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	MOVW	R8, R10		/* oldhi = hi */
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	SUBU	$1, R4
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	BNE	R4, _mulsubloop
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	MOVW	0(R6), R11	/* tmp = p[i] */
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	SUBU	R10, R11, R3	/* tmp -= oldhi */
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	MOVW	R3, 0(R6)	/* p[i] = tmp */
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	SGTU	R3, R11, R1
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	BNE	R1, _mulsub2
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	MOVW	$1, R1		/* return +1 for positive result */
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	RET
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_mulsub2:
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	MOVW	$-1, R1		/* return -1 for negative result */
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	RET