Subversion Repositories planix.SVN

Rev

Rev 2 | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
2 - 1 
.TH GETFCR 2
2 
.SH NAME
3 
getfcr, setfcr, getfsr, setfsr \- control floating point
4 
.SH SYNOPSIS
5 
.B #include <u.h>
6 
.br
7 
.B #include <libc.h>
8 
.PP
9 
.B
10 
ulong getfcr(void)
11 
.PP
12 
.B
13 
void setfcr(ulong fcr)
14 
.PP
15 
.B
16 
ulong getfsr(void)
17 
.PP
18 
.B
19 
void setfsr(ulong fsr)
20 
.SH DESCRIPTION
21 
These routines provide a fairly portable interface to control the
22 
rounding and exception characteristics of IEEE 754 floating point units.
23 
In effect, they define a pair of pseudo-registers, the floating
24 
point control register,
25 
.BR fcr ,
26 
which affects rounding, precision, and exceptions, and the
27 
floating point status register,
28 
.BR fsr ,
29 
which holds the accrued exception bits.
30 
Each register has a
31 
.I get
32 
routine to retrieve its value, a
33 
.I set
34 
routine to modify it,
35 
and macros that identify its contents.
36 
.PP
37 
The
38 
.B fcr
39 
contains bits that, when set, halt execution upon exceptions:
40 
.B FPINEX
41 
(enable inexact exceptions),
42 
.B FPOVFL
43 
(enable overflow exceptions),
44 
.B FPUNFL
45 
(enable underflow exceptions),
46 
.B FPZDIV
47 
(enable zero divide exceptions), and
48 
.B FPINVAL
49 
(enable invalid operation exceptions).
50 
Rounding is controlled by installing in
51 
.BR fcr ,
52 
under mask
53 
.BR FPRMASK ,
54 
one of the values
55 
.B FPRNR
56 
(round to nearest),
57 
.B FPRZ
58 
(round towards zero),
59 
.B FPRPINF
60 
(round towards positive infinity), and
61 
.B FPRNINF
62 
(round towards negative infinity).
63 
Precision is controlled by installing in
64 
.BR fcr ,
65 
under mask
66 
.BR FPPMASK ,
67 
one of the values
68 
.B FPPEXT
69 
(extended precision),
70 
.B FPPSGL
71 
(single precision), and
72 
.B FPPDBL
73 
(double precision).
74 
.PP
75 
The
76 
.B fsr
77 
holds the accrued exception bits
78 
.BR FPAINEX ,
79 
.BR FPAOVFL ,
80 
.BR FPAUNFL ,
81 
.BR FPAZDIV ,
82 
and
83 
.BR FPAINVAL ,
84 
corresponding to the
85 
.B fsr
86 
bits without the
87 
.B A
88 
in the name.
89 
.PP
90 
Not all machines support all modes.  If the corresponding mask
91 
is zero, the machine does not support the rounding or precision modes.
92 
On some machines it is not possible to clear selective accrued
93 
exception bits; a
94 
.I setfsr
95 
clears them all.
96 
The exception bits defined here work on all architectures.
97 
Where possible, the initial state is equivalent to
98 
.IP
99 
.EX
100 
setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL);
101 
.EE
102 
.PP
103 
However, this may vary between architectures:
104 
the default is to provide what the hardware does most efficiently.
105 
Use these routines
106 
if you need guaranteed behavior.
107 
Also, gradual underflow is not available on some machines.
108 
.SH EXAMPLE
109 
To enable overflow traps and make sure registers are rounded
110 
to double precision (for example on the MC68020, where the
111 
internal registers are 80 bits long):
112 
.EX
113 
.IP
114 
.ft L
115 
setfcr((getfcr() & ~FPPMASK) | FPPDBL | FPOVFL);
116 
.ft
117 
.EE
118 
.SH SOURCE
119 
.B /sys/src/libc/$objtype/getfcr.s