Subversion Repositories planix.SVN

Rev

Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
2 - 1 
/*
2 
 * USB host driver for BCM2835
3 
 *	Synopsis DesignWare Core USB 2.0 OTG controller
4 
 *
5 
 * Device register definitions
6 
 */
7 
 
8 
typedef unsigned int Reg;
9 
typedef struct Dwcregs Dwcregs;
10 
typedef struct Hostchan Hostchan;
11 
 
12 
enum {
13 
	Maxchans	= 16,	/* actual number of channels in ghwcfg2 */
14 
};
15 
 
16 
struct Dwcregs {
17 
	/* Core global registers 0x000-0x140 */
18 
	Reg	gotgctl;	/* OTG Control and Status */
19 
	Reg	gotgint;	/* OTG Interrupt */
20 
	Reg	gahbcfg;	/* Core AHB Configuration */
21 
	Reg	gusbcfg;	/* Core USB Configuration */
22 
	Reg	grstctl;	/* Core Reset */
23 
	Reg	gintsts;	/* Core Interrupt */
24 
	Reg	gintmsk;	/* Core Interrupt Mask */
25 
	Reg	grxstsr;	/* Receive Status Queue Read (RO) */
26 
	Reg	grxstsp;	/* Receive Status Queue Read & POP (RO) */
27 
	Reg	grxfsiz;	/* Receive FIFO Size */
28 
	Reg	gnptxfsiz;	/* Non Periodic Transmit FIFO Size */
29 
	Reg	gnptxsts;	/* Non Periodic Transmit FIFO/Queue Status (RO) */
30 
	Reg	gi2cctl;	/* I2C Access */
31 
	Reg	gpvndctl;	/* PHY Vendor Control */
32 
	Reg	ggpio;		/* General Purpose Input/Output */
33 
	Reg	guid;		/* User ID */
34 
	Reg	gsnpsid;	/* Synopsys ID (RO) */
35 
	Reg	ghwcfg1;	/* User HW Config1 (RO) (DEVICE) */
36 
	Reg	ghwcfg2;	/* User HW Config2 (RO) */
37 
	Reg	ghwcfg3;	/* User HW Config3 (RO) */
38 
	Reg	ghwcfg4;	/* User HW Config4 (RO)*/
39 
	Reg	glpmcfg;	/* Core LPM Configuration */
40 
	Reg	gpwrdn;		/* Global PowerDn */
41 
	Reg	gdfifocfg;	/* Global DFIFO SW Config (DEVICE?) */
42 
	Reg	adpctl;		/* ADP Control */
43 
	Reg	reserved0[39];
44 
	Reg	hptxfsiz;	/* Host Periodic Transmit FIFO Size */
45 
	Reg	dtxfsiz[15];	/* Device Periodic Transmit FIFOs (DEVICE) */
46 
	char	pad0[0x400-0x140];
47 
 
48 
	/* Host global registers 0x400-0x420 */
49 
	Reg	hcfg;		/* Configuration */
50 
	Reg	hfir;		/* Frame Interval */
51 
	Reg	hfnum;		/* Frame Number / Frame Remaining (RO) */
52 
	Reg	reserved1;
53 
	Reg	hptxsts;	/* Periodic Transmit FIFO / Queue Status */
54 
	Reg	haint;		/* All Channels Interrupt */
55 
	Reg	haintmsk;	/* All Channels Interrupt Mask */
56 
	Reg	hflbaddr;	/* Frame List Base Address */
57 
	char	pad1[0x440-0x420];
58 
 
59 
	/* Host port register 0x440 */
60 
	Reg	hport0;		/* Host Port 0 Control and Status */
61 
	char	pad2[0x500-0x444];
62 
 
63 
	/* Host channel specific registers 0x500-0x700 */
64 
	struct	Hostchan {
65 
		Reg	hcchar;	/* Characteristic */
66 
		Reg	hcsplt;	/* Split Control */
67 
		Reg	hcint;	/* Interrupt */
68 
		Reg	hcintmsk; /* Interrupt Mask */
69 
		Reg	hctsiz;	/* Transfer Size */
70 
		Reg	hcdma;	/* DMA Address */
71 
		Reg	reserved;
72 
		Reg	hcdmab;	/* DMA Buffer Address */
73 
	} hchan[Maxchans];
74 
	char	pad3[0xE00-0x700];
75 
 
76 
	/* Power & clock gating control register 0xE00 */
77 
	Reg	pcgcctl;
78 
};
79 
 
80 
enum {
81 
	/* gotgctl */
82 
	Sesreqscs	= 1<<0,
83 
	Sesreq		= 1<<1,
84 
	Vbvalidoven	= 1<<2,
85 
	Vbvalidovval	= 1<<3,
86 
	Avalidoven	= 1<<4,
87 
	Avalidovval	= 1<<5,
88 
	Bvalidoven	= 1<<6,
89 
	Bvalidovval	= 1<<7,
90 
	Hstnegscs	= 1<<8,
91 
	Hnpreq		= 1<<9,
92 
	Hstsethnpen	= 1<<10,
93 
	Devhnpen	= 1<<11,
94 
	Conidsts	= 1<<16,
95 
	Dbnctime	= 1<<17,
96 
	Asesvld		= 1<<18,
97 
	Bsesvld		= 1<<19,
98 
	Otgver		= 1<<20,
99 
	Multvalidbc	= 0x1F<<22,
100 
	Chirpen		= 1<<27,
101 
 
102 
	/* gotgint */
103 
	Sesenddet	= 1<<2,
104 
	Sesreqsucstschng= 1<<8,
105 
	Hstnegsucstschng= 1<<9,
106 
	Hstnegdet	= 1<<17,
107 
	Adevtoutchng	= 1<<18,
108 
	Debdone		= 1<<19,
109 
	Mvic		= 1<<20,
110 
 
111 
	/* gahbcfg */
112 
	Glblintrmsk	= 1<<0,
113 
	/* bits 1:4 redefined for BCM2835 */
114 
	Axiburstlen	= 0x3<<1,
115 
		BURST1		= 3<<1,
116 
		BURST2		= 2<<1,
117 
		BURST3		= 1<<1,
118 
		BURST4		= 0<<1,
119 
	Axiwaitwrites	= 1<<4,
120 
	Dmaenable	= 1<<5,
121 
	Nptxfemplvl	= 1<<7,
122 
		NPTX_HALFEMPTY	= 0<<7,
123 
		NPTX_EMPTY	= 1<<7,
124 
	Ptxfemplvl	= 1<<8,
125 
		PTX_HALFEMPTY	= 0<<8,
126 
		PTX_EMPTY	= 1<<8,
127 
	Remmemsupp	= 1<<21,
128 
	Notialldmawrit	= 1<<22,
129 
	Ahbsingle	= 1<<23,
130 
 
131 
	/* gusbcfg */
132 
	Toutcal		= 0x7<<0,
133 
	Phyif		= 1<<3,
134 
	Ulpi_utmi_sel	= 1<<4,
135 
	Fsintf		= 1<<5,
136 
		FsUnidir	= 0<<5,
137 
		FsBidir		= 1<<5,
138 
	Physel		= 1<<6,
139 
		PhyHighspeed	= 0<<6,
140 
		PhyFullspeed	= 1<<6,
141 
	Ddrsel		= 1<<7,
142 
	Srpcap		= 1<<8,
143 
	Hnpcap		= 1<<9,
144 
	Usbtrdtim	= 0xf<<10,
145 
		OUsbtrdtim		= 10,
146 
	Phylpwrclksel	= 1<<15,
147 
	Otgutmifssel	= 1<<16,
148 
	Ulpi_fsls	= 1<<17,
149 
	Ulpi_auto_res	= 1<<18,
150 
	Ulpi_clk_sus_m	= 1<<19,
151 
	Ulpi_ext_vbus_drv= 1<<20,
152 
	Ulpi_int_vbus_indicator= 1<<21,
153 
	Term_sel_dl_pulse= 1<<22,
154 
	Indicator_complement= 1<<23,
155 
	Indicator_pass_through= 1<<24,
156 
	Ulpi_int_prot_dis= 1<<25,
157 
	Ic_usb_cap	= 1<<26,
158 
	Ic_traffic_pull_remove= 1<<27,
159 
	Tx_end_delay	= 1<<28,
160 
	Force_host_mode	= 1<<29,
161 
	Force_dev_mode	= 1<<30,
162 
 
163 
	/* grstctl */
164 
	Csftrst		= 1<<0,
165 
	Hsftrst		= 1<<1,
166 
	Hstfrm		= 1<<2,
167 
	Intknqflsh	= 1<<3,
168 
	Rxfflsh		= 1<<4,
169 
	Txfflsh		= 1<<5,
170 
	Txfnum		= 0x1f<<6,
171 
		TXF_ALL		= 0x10<<6,
172 
	Dmareq		= 1<<30,
173 
	Ahbidle		= 1<<31,
174 
 
175 
	/* gintsts, gintmsk */
176 
	Curmode		= 1<<0,
177 
		HOSTMODE	= 1<<0,
178 
		DEVMODE		= 0<<0,
179 
	Modemismatch	= 1<<1,
180 
	Otgintr		= 1<<2,
181 
	Sofintr		= 1<<3,
182 
	Rxstsqlvl	= 1<<4,
183 
	Nptxfempty	= 1<<5,
184 
	Ginnakeff	= 1<<6,
185 
	Goutnakeff	= 1<<7,
186 
	Ulpickint	= 1<<8,
187 
	I2cintr		= 1<<9,
188 
	Erlysuspend	= 1<<10,
189 
	Usbsuspend	= 1<<11,
190 
	Usbreset	= 1<<12,
191 
	Enumdone	= 1<<13,
192 
	Isooutdrop	= 1<<14,
193 
	Eopframe	= 1<<15,
194 
	Restoredone	= 1<<16,
195 
	Epmismatch	= 1<<17,
196 
	Inepintr	= 1<<18,
197 
	Outepintr	= 1<<19,
198 
	Incomplisoin	= 1<<20,
199 
	Incomplisoout	= 1<<21,
200 
	Fetsusp		= 1<<22,
201 
	Resetdet	= 1<<23,
202 
	Portintr	= 1<<24,
203 
	Hcintr		= 1<<25,
204 
	Ptxfempty	= 1<<26,
205 
	Lpmtranrcvd	= 1<<27,
206 
	Conidstschng	= 1<<28,
207 
	Disconnect	= 1<<29,
208 
	Sessreqintr	= 1<<30,
209 
	Wkupintr	= 1<<31,
210 
 
211 
	/* grxsts[rp] */
212 
	Chnum		= 0xf<<0,
213 
	Bcnt		= 0x7ff<<4,
214 
	Dpid		= 0x3<<15,
215 
	Pktsts		= 0xf<<17,
216 
		PKTSTS_IN		= 2<<17,
217 
		PKTSTS_IN_XFER_COMP	= 3<<17,
218 
		PKTSTS_DATA_TOGGLE_ERR	= 5<<17,
219 
		PKTSTS_CH_HALTED	= 7<<17,
220 
 
221 
	/* hptxfsiz, gnptxfsiz */
222 
	Startaddr	= 0xffff<<0,
223 
	Depth		= 0xffff<<16,
224 
		ODepth		= 16,
225 
 
226 
	/* gnptxsts */
227 
	Nptxfspcavail	= 0xffff<<0,
228 
	Nptxqspcavail	= 0xff<<16,
229 
	Nptxqtop_terminate= 1<<24,
230 
	Nptxqtop_token	= 0x3<<25,
231 
	Nptxqtop_chnep	= 0xf<<27,
232 
 
233 
	/* gpvndctl */
234 
	Regdata		= 0xff<<0,
235 
	Vctrl		= 0xff<<8,
236 
	Regaddr16_21	= 0x3f<<16,
237 
	Regwr		= 1<<22,
238 
	Newregreq	= 1<<25,
239 
	Vstsbsy		= 1<<26,
240 
	Vstsdone	= 1<<27,
241 
	Disulpidrvr	= 1<<31,
242 
 
243 
	/* ggpio */
244 
	Gpi		= 0xffff<<0,
245 
	Gpo		= 0xffff<<16,
246 
 
247 
	/* ghwcfg2 */
248 
	Op_mode		= 0x7<<0,
249 
		HNP_SRP_CAPABLE_OTG	= 0<<0,
250 
		SRP_ONLY_CAPABLE_OTG	= 1<<0,
251 
		NO_HNP_SRP_CAPABLE	= 2<<0,
252 
		SRP_CAPABLE_DEVICE	= 3<<0,
253 
		NO_SRP_CAPABLE_DEVICE	= 4<<0,
254 
		SRP_CAPABLE_HOST	= 5<<0,
255 
		NO_SRP_CAPABLE_HOST	= 6<<0,
256 
	Architecture	= 0x3<<3,
257 
		SLAVE_ONLY		= 0<<3,
258 
		EXT_DMA			= 1<<3,
259 
		INT_DMA			= 2<<3,
260 
	Point2point	= 1<<5,
261 
	Hs_phy_type	= 0x3<<6,
262 
		PHY_NOT_SUPPORTED	= 0<<6,
263 
		PHY_UTMI		= 1<<6,
264 
		PHY_ULPI		= 2<<6,
265 
		PHY_UTMI_ULPI		= 3<<6,
266 
	Fs_phy_type	= 0x3<<8,
267 
	Num_dev_ep	= 0xf<<10,
268 
	Num_host_chan	= 0xf<<14,
269 
		ONum_host_chan		= 14,
270 
	Perio_ep_supported= 1<<18,
271 
	Dynamic_fifo	= 1<<19,
272 
	Nonperio_tx_q_depth= 0x3<<22,
273 
	Host_perio_tx_q_depth= 0x3<<24,
274 
	Dev_token_q_depth= 0x1f<<26,
275 
	Otg_enable_ic_usb= 1<<31,
276 
 
277 
	/* ghwcfg3 */
278 
	Xfer_size_cntr_width	= 0xf<<0,
279 
	Packet_size_cntr_width	= 0x7<<4,
280 
	Otg_func		= 1<<7,
281 
	I2c			= 1<<8,
282 
	Vendor_ctrl_if		= 1<<9,
283 
	Optional_features	= 1<<10,
284 
	Synch_reset_type	= 1<<11,
285 
	Adp_supp		= 1<<12,
286 
	Otg_enable_hsic		= 1<<13,
287 
	Bc_support		= 1<<14,
288 
	Otg_lpm_en		= 1<<15,
289 
	Dfifo_depth		= 0xffff<<16,
290 
		ODfifo_depth		= 16,
291 
 
292 
	/* ghwcfg4 */
293 
	Num_dev_perio_in_ep	= 0xf<<0,
294 
	Power_optimiz		= 1<<4,
295 
	Min_ahb_freq		= 1<<5,
296 
	Hiber			= 1<<6,
297 
	Xhiber			= 1<<7,
298 
	Utmi_phy_data_width	= 0x3<<14,
299 
	Num_dev_mode_ctrl_ep	= 0xf<<16,
300 
	Iddig_filt_en		= 1<<20,
301 
	Vbus_valid_filt_en	= 1<<21,
302 
	A_valid_filt_en		= 1<<22,
303 
	B_valid_filt_en		= 1<<23,
304 
	Session_end_filt_en	= 1<<24,
305 
	Ded_fifo_en		= 1<<25,
306 
	Num_in_eps		= 0xf<<26,
307 
	Desc_dma		= 1<<30,
308 
	Desc_dma_dyn		= 1<<31,
309 
 
310 
	/* glpmcfg */
311 
	Lpm_cap_en	= 1<<0,
312 
	Appl_resp	= 1<<1,
313 
	Hird		= 0xf<<2,
314 
	Rem_wkup_en	= 1<<6,
315 
	En_utmi_sleep	= 1<<7,
316 
	Hird_thres	= 0x1f<<8,
317 
	Lpm_resp	= 0x3<<13,
318 
	Prt_sleep_sts	= 1<<15,
319 
	Sleep_state_resumeok= 1<<16,
320 
	Lpm_chan_index	= 0xf<<17,
321 
	Retry_count	= 0x7<<21,
322 
	Send_lpm	= 1<<24,
323 
	Retry_count_sts	= 0x7<<25,
324 
	Hsic_connect	= 1<<30,
325 
	Inv_sel_hsic	= 1<<31,
326 
 
327 
	/* gpwrdn */
328 
	Pmuintsel	= 1<<0,
329 
	Pmuactv		= 1<<1,
330 
	Restore		= 1<<2,
331 
	Pwrdnclmp	= 1<<3,
332 
	Pwrdnrstn	= 1<<4,
333 
	Pwrdnswtch	= 1<<5,
334 
	Dis_vbus	= 1<<6,
335 
	Lnstschng	= 1<<7,
336 
	Lnstchng_msk	= 1<<8,
337 
	Rst_det		= 1<<9,
338 
	Rst_det_msk	= 1<<10,
339 
	Disconn_det	= 1<<11,
340 
	Disconn_det_msk	= 1<<12,
341 
	Connect_det	= 1<<13,
342 
	Connect_det_msk	= 1<<14,
343 
	Srp_det		= 1<<15,
344 
	Srp_det_msk	= 1<<16,
345 
	Sts_chngint	= 1<<17,
346 
	Sts_chngint_msk	= 1<<18,
347 
	Linestate	= 0x3<<19,
348 
	Idsts		= 1<<21,
349 
	Bsessvld	= 1<<22,
350 
	Adp_int		= 1<<23,
351 
	Mult_val_id_bc	= 0x1f<<24,
352 
 
353 
	/* gdfifocfg */
354 
	Gdfifocfg	= 0xffff<<0,
355 
	Epinfobase	= 0xffff<<16,
356 
 
357 
	/* adpctl */
358 
	Prb_dschg	= 0x3<<0,
359 
	Prb_delta	= 0x3<<2,
360 
	Prb_per		= 0x3<<4,
361 
	Rtim		= 0x7ff<<6,
362 
	Enaprb		= 1<<17,
363 
	Enasns		= 1<<18,
364 
	Adpres		= 1<<19,
365 
	Adpen		= 1<<20,
366 
	Adp_prb_int	= 1<<21,
367 
	Adp_sns_int	= 1<<22,
368 
	Adp_tmout_int	= 1<<23,
369 
	Adp_prb_int_msk	= 1<<24,
370 
	Adp_sns_int_msk	= 1<<25,
371 
	Adp_tmout_int_msk= 1<<26,
372 
	Ar		= 0x3<<27,
373 
 
374 
	/* hcfg */
375 
	Fslspclksel	= 0x3<<0,
376 
		HCFG_30_60_MHZ	= 0<<0,
377 
		HCFG_48_MHZ	= 1<<0,
378 
		HCFG_6_MHZ	= 2<<0,
379 
	Fslssupp	= 1<<2,
380 
	Ena32khzs	= 1<<7,
381 
	Resvalid	= 0xff<<8,
382 
	Descdma		= 1<<23,
383 
	Frlisten	= 0x3<<24,
384 
	Modechtimen	= 1<<31,
385 
 
386 
	/* hfir */
387 
	Frint		= 0xffff<<0,
388 
	Hfirrldctrl	= 1<<16,
389 
 
390 
	/* hfnum */
391 
	Frnum		= 0xffff<<0,
392 
		MAX_FRNUM 	= 0x3FFF<<0,
393 
	Frrem		= 0xffff<<16,
394 
 
395 
	/* hptxsts */
396 
	Ptxfspcavail	= 0xffff<<0,
397 
	Ptxqspcavail	= 0xff<<16,
398 
	Ptxqtop_terminate= 1<<24,
399 
	Ptxqtop_token	= 0x3<<25,
400 
	Ptxqtop_chnum	= 0xf<<27,
401 
	Ptxqtop_odd	= 1<<31,
402 
 
403 
	/* haint, haintmsk */
404 
#define CHANINT(n)	(1<<(n))
405 
 
406 
	/* hport0 */
407 
	Prtconnsts	= 1<<0,		/* connect status (RO) */
408 
	Prtconndet	= 1<<1,		/* connect detected R/W1C) */
409 
	Prtena		= 1<<2,		/* enable (R/W1C) */
410 
	Prtenchng	= 1<<3,		/* enable/disable change (R/W1C) */
411 
	Prtovrcurract	= 1<<4,		/* overcurrent active (RO) */
412 
	Prtovrcurrchng	= 1<<5,		/* overcurrent change (R/W1C) */
413 
	Prtres		= 1<<6,		/* resume */
414 
	Prtsusp		= 1<<7,		/* suspend */
415 
	Prtrst		= 1<<8,		/* reset */
416 
	Prtlnsts	= 0x3<<10,	/* line state {D+,D-} (RO) */
417 
	Prtpwr		= 1<<12,	/* power on */
418 
	Prttstctl	= 0xf<<13,	/* test */
419 
	Prtspd		= 0x3<<17,	/* speed (RO) */
420 
		HIGHSPEED	= 0<<17,
421 
		FULLSPEED	= 1<<17,
422 
		LOWSPEED	= 2<<17,
423 
 
424 
	/* hcchar */
425 
	Mps		= 0x7ff<<0,	/* endpoint maximum packet size */
426 
	Epnum		= 0xf<<11,	/* endpoint number */
427 
		OEpnum		= 11,
428 
	Epdir		= 1<<15,	/* endpoint direction */
429 
		Epout		= 0<<15,
430 
		Epin		= 1<<15,
431 
	Lspddev		= 1<<17,	/* device is lowspeed */
432 
	Eptype		= 0x3<<18,	/* endpoint type */
433 
		Epctl		= 0<<18,
434 
		Episo		= 1<<18,
435 
		Epbulk		= 2<<18,
436 
		Epintr		= 3<<18,
437 
	Multicnt	= 0x3<<20,	/* transactions per μframe */
438 
					/* or retries per periodic split */
439 
		OMulticnt	= 20,
440 
	Devaddr		= 0x7f<<22,	/* device address */
441 
		ODevaddr	= 22,
442 
	Oddfrm		= 1<<29,	/* xfer in odd frame (iso/interrupt) */
443 
	Chdis		= 1<<30,	/* channel disable (write 1 only) */
444 
	Chen		= 1<<31,	/* channel enable (write 1 only) */
445 
 
446 
	/* hcsplt */
447 
	Prtaddr		= 0x7f<<0,	/* port address of recipient */
448 
					/* transaction translator */
449 
	Hubaddr		= 0x7f<<7,	/* dev address of transaction */
450 
					/* translator's hub */
451 
		OHubaddr	= 7,
452 
	Xactpos		= 0x3<<14,	/* payload's position within transaction */
453 
		POS_MID		= 0<<14,
454 
		POS_END		= 1<<14,
455 
		POS_BEGIN	= 2<<14,
456 
		POS_ALL		= 3<<14, /* all of data (<= 188 bytes) */
457 
	Compsplt	= 1<<16,	/* do complete split */
458 
	Spltena		= 1<<31,	/* channel enabled to do splits */
459 
 
460 
	/* hcint, hcintmsk */
461 
	Xfercomp	= 1<<0,		/* transfer completed without error */
462 
	Chhltd		= 1<<1,		/* channel halted */
463 
	Ahberr		= 1<<2,		/* AHB dma error */
464 
	Stall		= 1<<3,
465 
	Nak		= 1<<4,
466 
	Ack		= 1<<5,
467 
	Nyet		= 1<<6,
468 
	Xacterr		= 1<<7,	/* transaction error (crc, t/o, bit stuff, eop) */
469 
	Bblerr		= 1<<8,
470 
	Frmovrun	= 1<<9,
471 
	Datatglerr	= 1<<10,
472 
	Bna		= 1<<11,
473 
	Xcs_xact	= 1<<12,
474 
	Frm_list_roll	= 1<<13,
475 
 
476 
	/* hctsiz */
477 
	Xfersize	= 0x7ffff<<0,	/* expected total bytes */
478 
	Pktcnt		= 0x3ff<<19,	/* expected number of packets */
479 
		OPktcnt		= 19,
480 
	Pid		= 0x3<<29,	/* packet id for initial transaction */
481 
		DATA0		= 0<<29,
482 
		DATA1		= 2<<29,	/* sic */
483 
		DATA2		= 1<<29,	/* sic */
484 
		MDATA		= 3<<29,	/* (non-ctl ep) */
485 
		SETUP		= 3<<29,	/* (ctl ep) */
486 
	Dopng		= 1<<31,	/* do PING protocol */
487 
 
488 
	/* pcgcctl */
489 
	Stoppclk		= 1<<0,
490 
	Gatehclk		= 1<<1,
491 
	Pwrclmp			= 1<<2,
492 
	Rstpdwnmodule		= 1<<3,
493 
	Enbl_sleep_gating	= 1<<5,
494 
	Phy_in_sleep		= 1<<6,
495 
	Deep_sleep		= 1<<7,
496 
	Resetaftsusp		= 1<<8,
497 
	Restoremode		= 1<<9,
498 
	Enbl_extnd_hiber	= 1<<10,
499 
	Extnd_hiber_pwrclmp	= 1<<11,
500 
	Extnd_hiber_switch	= 1<<12,
501 
	Ess_reg_restored	= 1<<13,
502 
	Prt_clk_sel		= 0x3<<14,
503 
	Port_power		= 1<<16,
504 
	Max_xcvrselect		= 0x3<<17,
505 
	Max_termsel		= 1<<19,
506 
	Mac_dev_addr		= 0x7f<<20,
507 
	P2hd_dev_enum_spd	= 0x3<<27,
508 
	P2hd_prt_spd		= 0x3<<29,
509 
	If_dev_mode		= 1<<31,
510 
};