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/*
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* sheevaplug machine assist, definitions
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* arm926ej-s processor at 1.2GHz
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*
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* loader uses R11 as scratch.
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*/
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#include "mem.h"
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#include "arm.h"
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#undef B /* B is for 'botch' */
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#define PADDR(a) ((a) & ~KZERO)
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#define KADDR(a) (KZERO|(a))
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#define L1X(va) (((((va))>>20) & 0x0fff)<<2)
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#define MACHADDR (L1-MACHSIZE)
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#define PTEDRAM (Dom0|L1AP(Krw)|Section|Cached|Buffered)
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#define PTEIO (Dom0|L1AP(Krw)|Section)
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/* wave at the user; clobbers R1 & R7; needs R12 (SB) set */
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#define PUTC(c) \
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ISB; \
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MOVW $PHYSCONS, R7; \
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MOVW $(c), R1; \
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MOVW R1, (R7); \
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ISB
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/* new instructions */
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#define CLZ(s, d) WORD $(0xe16f0f10 | (d) << 12 | (s)) /* count leading 0s */
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#define DMB \
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEdmbarr
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/*
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* data synchronisation barrier (formerly drain write buffer).
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* waits for cache flushes, eviction buffer drain, tlb flushes,
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* branch-prediction flushes, writes to memory; the lot.
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* on sheeva, also flushes L2 eviction buffer.
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* zeroes R0.
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*/
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#define DSB \
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MOVW $0, R0; \
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
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/*
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* prefetch flush; zeroes R0.
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* arm926ej-s manual says we need to sync with l2 cache in isb,
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* and uncached load is the easiest way. doesn't seem to matter.
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*/
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#define ISB \
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MOVW $0, R0; \
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEwait
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// MOVW (R0), R0; MOVW $0, R0
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/* zeroes R0 */
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#define BARRIERS ISB; DSB
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/*
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* invoked with PTE bits in R2, pa in R3, PTE pointed to by R4.
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* fill PTE pointed to by R4 and increment R4 past it.
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* increment R3 by a MB. clobbers R1.
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*/
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#define FILLPTE() \
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ORR R3, R2, R1; /* pte bits in R2, pa in R3 */ \
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MOVW R1, (R4); \
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ADD $4, R4; /* bump PTE address */ \
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ADD $MiB, R3; /* bump pa */ \
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/* zero PTE pointed to by R4 and increment R4 past it. assumes R0 is 0. */
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#define ZEROPTE() \
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MOVW R0, (R4); \
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ADD $4, R4; /* bump PTE address */
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