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/*
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* sheevaplug reboot code
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*
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* R11 is used by the loader as a temporary, so avoid it.
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*/
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#include "arm.s"
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/*
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* Turn off MMU, then copy the new kernel to its correct location
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* in physical memory. Then jump to the start of the kernel.
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*/
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/* main(PADDR(entry), PADDR(code), size); */
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TEXT main(SB), 1, $-4
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MOVW $setR12(SB), R12
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MOVW R0, p1+0(FP) /* destination, passed in R0 */
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/* copy in arguments from frame */
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MOVW R0, R8 /* entry point */
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MOVW p2+4(FP), R9 /* source */
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MOVW n+8(FP), R10 /* byte count */
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PUTC('R')
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BL cachesoff(SB)
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/* now back in 29- or 26-bit addressing, mainly for SB */
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/* turn the MMU off */
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PUTC('e')
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MOVW $KSEGM, R7
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MOVW $PHYSDRAM, R0
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BL _r15warp(SB)
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BIC R7, R12 /* SB */
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BIC R7, R13 /* SP */
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/* don't care about R14 */
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PUTC('b')
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BL mmuinvalidate(SB)
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PUTC('o')
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BL mmudisable(SB)
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PUTC('o')
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MOVW R9, R4 /* restore regs across function calls */
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MOVW R10, R5
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MOVW R8, R6
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/* set up a new stack for local vars and memmove args */
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MOVW R6, SP /* tiny trampoline stack */
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SUB $(0x20 + 4), SP /* back up before a.out header */
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MOVW R14, -48(SP) /* store return addr */
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SUB $48, SP /* allocate stack frame */
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MOVW R6, 44(SP) /* save dest/entry */
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MOVW R5, 40(SP) /* save count */
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PUTC('t')
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MOVW R6, 0(SP)
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MOVW R6, 4(SP) /* push dest */
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MOVW R6, R0
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MOVW R4, 8(SP) /* push src */
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MOVW R5, 12(SP) /* push size */
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BL memmove(SB)
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MOVW 44(SP), R6 /* restore R6 (dest/entry) */
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MOVW 40(SP), R5 /* restore R5 (count) */
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PUTC('-')
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/*
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* flush caches
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*/
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BL cacheuwbinv(SB)
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PUTC('>')
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PUTC('\r');
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PUTC('\n');
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/*
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* jump to kernel entry point. Note the true kernel entry point is
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* the virtual address KZERO|R6, but this must wait until
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* the MMU is enabled by the kernel in l.s
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*/
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ORR R6, R6 /* NOP: avoid link bug */
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B (R6)
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/*
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* turn the caches off, double map 0 & KZERO, invalidate TLBs, revert to
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* tiny addresses. upon return, it will be safe to turn off the mmu.
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*/
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TEXT cachesoff(SB), 1, $-4
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R0
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MOVW R0, CPSR
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MOVW $KADDR(0x100-4), R7 /* just before this code */
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MOVW R14, (R7) /* save link */
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BL cacheuwbinv(SB)
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCwb|CpCicache|CpCdcache|CpCalign), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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/* redo double map of 0, KZERO */
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MOVW $(L1+L1X(PHYSDRAM)), R4 /* address of PTE for 0 */
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MOVW $PTEDRAM, R2 /* PTE bits */
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// MOVW $PTEIO, R2 /* PTE bits */
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MOVW $PHYSDRAM, R3
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MOVW $512, R5
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_ptrdbl:
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ORR R3, R2, R1 /* first identity-map 0 to 0, etc. */
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MOVW R1, (R4)
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ADD $4, R4 /* bump PTE address */
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ADD $MiB, R3 /* bump pa */
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SUB.S $1, R5
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BNE _ptrdbl
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BARRIERS
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvd), CpTLBinv
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* back to 29- or 26-bit addressing, mainly for SB */
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCd32|CpCi32), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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MOVW $KADDR(0x100-4), R7 /* just before this code */
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MOVW (R7), R14 /* restore link */
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RET
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TEXT _r15warp(SB), 1, $-4
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BIC $KSEGM, R14
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ORR R0, R14
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RET
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TEXT mmudisable(SB), 1, $-4
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpChv|CpCmmu|CpCdcache|CpCicache|CpCwb), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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RET
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TEXT mmuinvalidate(SB), 1, $-4 /* invalidate all */
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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RET
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TEXT cacheuwbinv(SB), 1, $-4 /* D+I writeback+invalidate */
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BARRIERS
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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_uwbinv: /* D writeback+invalidate */
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MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
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BNE _uwbinv
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MOVW $0, R0 /* I invalidate */
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
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BARRIERS
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
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BARRIERS
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MOVW R3, CPSR /* splx */
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RET
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