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/*
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* arm exception handlers
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*/
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#include "arm.s"
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#undef B /* B is for 'botch' */
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/*
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* exception vectors, copied by trapinit() to somewhere useful
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*/
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TEXT vectors(SB), 1, $-4
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MOVW 0x18(R15), R15 /* reset */
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MOVW 0x18(R15), R15 /* undefined instr. */
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MOVW 0x18(R15), R15 /* SWI & SMC */
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MOVW 0x18(R15), R15 /* prefetch abort */
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MOVW 0x18(R15), R15 /* data abort */
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MOVW 0x18(R15), R15 /* reserved */
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MOVW 0x18(R15), R15 /* IRQ */
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MOVW 0x18(R15), R15 /* FIQ */
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TEXT vtable(SB), 1, $-4
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WORD $_vsvc(SB) /* reset, in svc mode already */
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WORD $_vund(SB) /* undefined, switch to svc mode */
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WORD $_vsvc(SB) /* swi, in svc mode already */
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WORD $_vpabt(SB) /* prefetch abort, switch to svc mode */
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WORD $_vdabt(SB) /* data abort, switch to svc mode */
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WORD $_vsvc(SB) /* reserved */
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WORD $_virq(SB) /* IRQ, switch to svc mode */
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// WORD $_vfiq(SB) /* FIQ, switch to svc mode */
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WORD $_virq(SB) /* FIQ, switch to svc mode */
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TEXT _vrst(SB), 1, $-4
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BL _reset(SB)
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TEXT _vsvc(SB), 1, $-4 /* SWI */
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MOVW.W R14, -4(R13) /* ureg->pc = interrupted PC */
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MOVW SPSR, R14 /* ureg->psr = SPSR */
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MOVW.W R14, -4(R13) /* ... */
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MOVW $PsrMsvc, R14 /* ureg->type = PsrMsvc */
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MOVW.W R14, -4(R13) /* ... */
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/* avoid the ambiguity described in notes/movm.w. */
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// MOVM.DB.W.S [R0-R14], (R13) /* save user level registers, at end r13 points to ureg */
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MOVM.DB.S [R0-R14], (R13) /* save user level registers */
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SUB $(15*4), R13 /* r13 now points to ureg */
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MOVW $setR12(SB), R12 /* Make sure we've got the kernel's SB loaded */
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// MOVW $(KSEG0+16*KiB-MACHSIZE), R10 /* m */
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MOVW $(L1-MACHSIZE), R10 /* m */
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MOVW 8(R10), R9 /* up */
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MOVW R13, R0 /* first arg is pointer to ureg */
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SUB $8, R13 /* space for argument+link */
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BL syscall(SB)
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ADD $(8+4*15), R13 /* make r13 point to ureg->type */
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MOVW 8(R13), R14 /* restore link */
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MOVW 4(R13), R0 /* restore SPSR */
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MOVW R0, SPSR /* ... */
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MOVM.DB.S (R13), [R0-R14] /* restore registers */
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ADD $8, R13 /* pop past ureg->{type+psr} */
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RFE /* MOVM.IA.S.W (R13), [R15] */
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TEXT _vund(SB), 1, $-4 /* undefined */
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MOVM.IA [R0-R4], (R13) /* free some working space */
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MOVW $PsrMund, R0
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B _vswitch
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TEXT _vpabt(SB), 1, $-4 /* prefetch abort */
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MOVM.IA [R0-R4], (R13) /* free some working space */
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MOVW $PsrMabt, R0 /* r0 = type */
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B _vswitch
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TEXT _vdabt(SB), 1, $-4 /* data abort */
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MOVM.IA [R0-R4], (R13) /* free some working space */
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MOVW $(PsrMabt+1), R0 /* r0 = type */
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B _vswitch
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TEXT _virq(SB), 1, $-4 /* IRQ */
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MOVM.IA [R0-R4], (R13) /* free some working space */
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MOVW $PsrMirq, R0 /* r0 = type */
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B _vswitch
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/*
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* come here with type in R0 and R13 pointing above saved [r0-r4].
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* we'll switch to SVC mode and then call trap.
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*/
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_vswitch:
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MOVW SPSR, R1 /* save SPSR for ureg */
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MOVW R14, R2 /* save interrupted pc for ureg */
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MOVW R13, R3 /* save pointer to where the original [R0-R4] are */
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/*
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* switch processor to svc mode. this switches the banked registers
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* (r13 [sp] and r14 [link]) to those of svc mode.
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*/
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MOVW CPSR, R14
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BIC $PsrMask, R14
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ORR $(PsrDirq|PsrDfiq|PsrMsvc), R14
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MOVW R14, CPSR /* switch! */
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AND.S $0xf, R1, R4 /* interrupted code kernel or user? */
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BEQ _userexcep
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/* here for trap from SVC mode */
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MOVM.DB.W [R0-R2], (R13) /* set ureg->{type, psr, pc}; r13 points to ureg->type */
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MOVM.IA (R3), [R0-R4] /* restore [R0-R4] from previous mode's stack */
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/*
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* avoid the ambiguity described in notes/movm.w.
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* In order to get a predictable value in R13 after the stores,
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* separate the store-multiple from the stack-pointer adjustment.
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* We'll assume that the old value of R13 should be stored on the stack.
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*/
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/* save kernel level registers, at end r13 points to ureg */
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// MOVM.DB.W [R0-R14], (R13)
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MOVM.DB [R0-R14], (R13)
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SUB $(15*4), R13 /* SP now points to saved R0 */
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MOVW $setR12(SB), R12 /* Make sure we've got the kernel's SB loaded */
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MOVW R13, R0 /* first arg is pointer to ureg */
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SUB $(4*2), R13 /* space for argument+link (for debugger) */
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MOVW $0xdeaddead, R11 /* marker */
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BL trap(SB)
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ADD $(4*2+4*15), R13 /* make r13 point to ureg->type */
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MOVW 8(R13), R14 /* restore link */
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MOVW 4(R13), R0 /* restore SPSR */
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MOVW R0, SPSR /* ... */
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MOVM.DB (R13), [R0-R14] /* restore registers */
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ADD $(4*2), R13 /* pop past ureg->{type+psr} to pc */
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RFE /* MOVM.IA.S.W (R13), [R15] */
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/* here for trap from USER mode */
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_userexcep:
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MOVM.DB.W [R0-R2], (R13) /* set ureg->{type, psr, pc}; r13 points to ureg->type */
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MOVM.IA (R3), [R0-R4] /* restore [R0-R4] from previous mode's stack */
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/* avoid the ambiguity described in notes/movm.w. */
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// MOVM.DB.W.S [R0-R14], (R13) /* save kernel level registers, at end r13 points to ureg */
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MOVM.DB.S [R0-R14], (R13) /* save kernel level registers */
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SUB $(15*4), R13 /* r13 now points to ureg */
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MOVW $setR12(SB), R12 /* Make sure we've got the kernel's SB loaded */
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// MOVW $(KSEG0+16*KiB-MACHSIZE), R10 /* m */
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MOVW $(L1-MACHSIZE), R10 /* m */
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MOVW 8(R10), R9 /* up */
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MOVW R13, R0 /* first arg is pointer to ureg */
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SUB $(4*2), R13 /* space for argument+link (for debugger) */
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BL trap(SB)
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ADD $(4*2+4*15), R13 /* make r13 point to ureg->type */
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MOVW 8(R13), R14 /* restore link */
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MOVW 4(R13), R0 /* restore SPSR */
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MOVW R0, SPSR /* ... */
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MOVM.DB.S (R13), [R0-R14] /* restore registers */
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ADD $(4*2), R13 /* pop past ureg->{type+psr} */
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RFE /* MOVM.IA.S.W (R13), [R15] */
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TEXT _vfiq(SB), 1, $-4 /* FIQ */
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RFE /* FIQ is special, ignore it for now */
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/*
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* set the stack value for the mode passed in R0
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*/
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TEXT setr13(SB), 1, $-4
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MOVW 4(FP), R1
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MOVW CPSR, R2
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BIC $PsrMask, R2, R3
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ORR R0, R3
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MOVW R3, CPSR /* switch to new mode */
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MOVW R13, R0 /* return old sp */
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MOVW R1, R13 /* install new one */
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MOVW R2, CPSR /* switch back to old mode */
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RET
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