Subversion Repositories planix.SVN

/*

 * Etherlink III, Fast EtherLink and Fast EtherLink XL adapters.

 * To do:

 *	check robustness in the face of errors (e.g. busmaster & rxUnderrun);

 *	RxEarly and busmaster;

 *	autoSelect;

 *	PCI latency timer and master enable;

 *	errata list;

 *	rewrite all initialisation.

 */

#include "u.h"

#include "../port/lib.h"

#include "mem.h"

#include "dat.h"

#include "fns.h"

#include "io.h"

#include "../port/error.h"

#include "../port/netif.h"

#include "etherif.h"

#define XCVRDEBUG		if(0)print

enum {

	IDport			= 0x0110,	/* anywhere between 0x0100 and 0x01F0 */

};

enum {						/* all windows */

	CommandR		= 0x000E,

	IntStatusR		= 0x000E,

};

enum {						/* Commands */

	GlobalReset		= 0x0000,

	SelectRegisterWindow	= 0x0001,

	EnableDcConverter	= 0x0002,

	RxDisable		= 0x0003,

	RxEnable		= 0x0004,

	RxReset			= 0x0005,

	Stall			= 0x0006,	/* 3C90x */

	TxDone			= 0x0007,

	RxDiscard		= 0x0008,

	TxEnable		= 0x0009,

	TxDisable		= 0x000A,

	TxReset			= 0x000B,

	RequestInterrupt	= 0x000C,

	AcknowledgeInterrupt	= 0x000D,

	SetInterruptEnable	= 0x000E,

	SetIndicationEnable	= 0x000F,	/* SetReadZeroMask */

	SetRxFilter		= 0x0010,

	SetRxEarlyThresh	= 0x0011,

	SetTxAvailableThresh	= 0x0012,

	SetTxStartThresh	= 0x0013,

	StartDma		= 0x0014,	/* initiate busmaster operation */

	StatisticsEnable	= 0x0015,

	StatisticsDisable	= 0x0016,

	DisableDcConverter	= 0x0017,

	SetTxReclaimThresh	= 0x0018,	/* PIO-only adapters */

	PowerUp			= 0x001B,	/* not all adapters */

	PowerDownFull		= 0x001C,	/* not all adapters */

	PowerAuto		= 0x001D,	/* not all adapters */

};

enum {						/* (Global|Rx|Tx)Reset command bits */

	tpAuiReset		= 0x0001,	/* 10BaseT and AUI transceivers */

	endecReset		= 0x0002,	/* internal Ethernet encoder/decoder */

	networkReset		= 0x0004,	/* network interface logic */

	fifoReset		= 0x0008,	/* FIFO control logic */

	aismReset		= 0x0010,	/* autoinitialise state-machine logic */

	hostReset		= 0x0020,	/* bus interface logic */

	dmaReset		= 0x0040,	/* bus master logic */

	vcoReset		= 0x0080,	/* on-board 10Mbps VCO */

	updnReset		= 0x0100,	/* upload/download (Rx/TX) logic */

	resetMask		= 0x01FF,

};

enum {						/* Stall command bits */

	upStall			= 0x0000,

	upUnStall		= 0x0001,

	dnStall			= 0x0002,

	dnUnStall		= 0x0003,

};

enum {						/* SetRxFilter command bits */

	receiveIndividual	= 0x0001,	/* match station address */

	receiveMulticast	= 0x0002,

	receiveBroadcast	= 0x0004,

	receiveAllFrames	= 0x0008,	/* promiscuous */

};

enum {						/* StartDma command bits */

	Upload			= 0x0000,	/* transfer data from adapter to memory */

	Download		= 0x0001,	/* transfer data from memory to adapter */

};

enum {						/* IntStatus bits */

	interruptLatch		= 0x0001,

	hostError		= 0x0002,	/* Adapter Failure */

	txComplete		= 0x0004,

	txAvailable		= 0x0008,

	rxComplete		= 0x0010,

	rxEarly			= 0x0020,

	intRequested		= 0x0040,

	updateStats		= 0x0080,

	transferInt		= 0x0100,	/* Bus Master Transfer Complete */

	dnComplete		= 0x0200,

	upComplete		= 0x0400,

	busMasterInProgress	= 0x0800,

	commandInProgress	= 0x1000,

	interruptMask		= 0x07FE,

};

#define COMMAND(port, cmd, a)	outs((port)+CommandR, ((cmd)<<11)|(a))

#define STATUS(port)		ins((port)+IntStatusR)

enum {						/* Window 0 - setup */

	Wsetup			= 0x0000,

						/* registers */

	ManufacturerID		= 0x0000,	/* 3C5[08]*, 3C59[27] */

	ProductID		= 0x0002,	/* 3C5[08]*, 3C59[27] */

	ConfigControl		= 0x0004,	/* 3C5[08]*, 3C59[27] */

	AddressConfig		= 0x0006,	/* 3C5[08]*, 3C59[27] */

	ResourceConfig		= 0x0008,	/* 3C5[08]*, 3C59[27] */

	EepromCommand		= 0x000A,

	EepromData		= 0x000C,

						/* AddressConfig Bits */

	autoSelect9		= 0x0080,

	xcvrMask9		= 0xC000,

						/* ConfigControl bits */

	Ena			= 0x0001,

	base10TAvailable9	= 0x0200,

	coaxAvailable9		= 0x1000,

	auiAvailable9		= 0x2000,

						/* EepromCommand bits */

	EepromReadRegister	= 0x0080,

	EepromReadOffRegister	= 0x00B0,

	EepromRead8bRegister	= 0x0230,

	EepromBusy		= 0x8000,

};

#define EEPROMCMD(port, cmd, a)	outs((port)+EepromCommand, (cmd)|(a))

#define EEPROMBUSY(port)	(ins((port)+EepromCommand) & EepromBusy)

#define EEPROMDATA(port)	ins((port)+EepromData)

enum {						/* Window 1 - operating set */

	Wop			= 0x0001,

						/* registers */

	Fifo			= 0x0000,

	RxError			= 0x0004,	/* 3C59[0257] only */

	RxStatus		= 0x0008,

	TIMER			= 0x000A,

	TxStatus		= 0x000B,

	TxFree			= 0x000C,

						/* RxError bits */

	rxOverrun		= 0x0001,

	runtFrame		= 0x0002,

	alignmentError		= 0x0004,	/* Framing */

	crcError		= 0x0008,

	oversizedFrame		= 0x0010,

	dribbleBits		= 0x0080,

						/* RxStatus bits */

	rxBytes			= 0x1FFF,	/* 3C59[0257] mask */

	rxBytes9		= 0x07FF,	/* 3C5[078]9 mask */

	rxError9		= 0x3800,	/* 3C5[078]9 error mask */

	rxOverrun9		= 0x0000,

	oversizedFrame9		= 0x0800,

	dribbleBits9		= 0x1000,

	runtFrame9		= 0x1800,

	alignmentError9		= 0x2000,	/* Framing */

	crcError9		= 0x2800,

	rxError			= 0x4000,

	rxIncomplete		= 0x8000,

						/* TxStatus Bits */

	txStatusOverflow	= 0x0004,

	maxCollisions		= 0x0008,

	txUnderrun		= 0x0010,

	txJabber		= 0x0020,

	interruptRequested	= 0x0040,

	txStatusComplete	= 0x0080,

};

enum {						/* Window 2 - station address */

	Wstation		= 0x0002,

	ResetOp905B		= 0x000C,

};

enum {						/* Window 3 - FIFO management */

	Wfifo			= 0x0003,

						/* registers */

	InternalConfig		= 0x0000,	/* 3C509B, 3C589, 3C59[0257] */

	OtherInt		= 0x0004,	/* 3C59[0257] */

	RomControl		= 0x0006,	/* 3C509B, 3C59[27] */

	MacControl		= 0x0006,	/* 3C59[0257] */

	ResetOptions		= 0x0008,	/* 3C59[0257] */

	MediaOptions		= 0x0008,	/* 3C905B */

	RxFree			= 0x000A,

						/* InternalConfig bits */

	disableBadSsdDetect	= 0x00000100,

	ramLocation		= 0x00000200,	/* 0 external, 1 internal */

	ramPartition5to3	= 0x00000000,

	ramPartition3to1	= 0x00010000,

	ramPartition1to1	= 0x00020000,

	ramPartition3to5	= 0x00030000,

	ramPartitionMask	= 0x00030000,

	xcvr10BaseT		= 0x00000000,

	xcvrAui			= 0x00100000,	/* 10BASE5 */

	xcvr10Base2		= 0x00300000,

	xcvr100BaseTX		= 0x00400000,

	xcvr100BaseFX		= 0x00500000,

	xcvrMii			= 0x00600000,

	xcvrMask		= 0x00700000,

	autoSelect		= 0x01000000,

						/* MacControl bits */

	deferExtendEnable	= 0x0001,

	deferTIMERSelect	= 0x001E,	/* mask */

	fullDuplexEnable	= 0x0020,

	allowLargePackets	= 0x0040,

	extendAfterCollision	= 0x0080,	/* 3C90xB */

	flowControlEnable	= 0x0100,	/* 3C90xB */

	vltEnable		= 0x0200,	/* 3C90xB */

						/* ResetOptions bits */

	baseT4Available		= 0x0001,

	baseTXAvailable		= 0x0002,

	baseFXAvailable		= 0x0004,

	base10TAvailable	= 0x0008,

	coaxAvailable		= 0x0010,

	auiAvailable		= 0x0020,

	miiConnector		= 0x0040,

};

enum {						/* Window 4 - diagnostic */

	Wdiagnostic		= 0x0004,

						/* registers */

	VcoDiagnostic		= 0x0002,

	FifoDiagnostic		= 0x0004,

	NetworkDiagnostic	= 0x0006,

	PhysicalMgmt		= 0x0008,

	MediaStatus		= 0x000A,

	BadSSD			= 0x000C,

	UpperBytesOk		= 0x000D,

						/* FifoDiagnostic bits */

	txOverrun		= 0x0400,

	rxUnderrun		= 0x2000,

	receiving		= 0x8000,

						/* PhysicalMgmt bits */

	mgmtClk			= 0x0001,

	mgmtData		= 0x0002,

	mgmtDir			= 0x0004,

	cat5LinkTestDefeat	= 0x8000,

						/* MediaStatus bits */

	dataRate100		= 0x0002,

	crcStripDisable		= 0x0004,

	enableSqeStats		= 0x0008,

	collisionDetect		= 0x0010,

	carrierSense		= 0x0020,

	jabberGuardEnable	= 0x0040,

	linkBeatEnable		= 0x0080,

	jabberDetect		= 0x0200,

	polarityReversed	= 0x0400,

	linkBeatDetect		= 0x0800,

	txInProg		= 0x1000,

	dcConverterEnabled	= 0x4000,

	auiDisable		= 0x8000,	/* 10BaseT transceiver selected */

};

enum {						/* Window 5 - internal state */

	Wstate			= 0x0005,

						/* registers */

	TxStartThresh		= 0x0000,

	TxAvailableThresh	= 0x0002,

	RxEarlyThresh		= 0x0006,

	RxFilter		= 0x0008,

	InterruptEnable		= 0x000A,

	IndicationEnable	= 0x000C,

};

enum {						/* Window 6 - statistics */

	Wstatistics		= 0x0006,

						/* registers */

	CarrierLost		= 0x0000,

	SqeErrors		= 0x0001,

	MultipleColls		= 0x0002,

	SingleCollFrames	= 0x0003,

	LateCollisions		= 0x0004,

	RxOverruns		= 0x0005,

	FramesXmittedOk		= 0x0006,

	FramesRcvdOk		= 0x0007,

	FramesDeferred		= 0x0008,

	UpperFramesOk		= 0x0009,

	BytesRcvdOk		= 0x000A,

	BytesXmittedOk		= 0x000C,

};

enum {						/* Window 7 - bus master operations */

	Wmaster			= 0x0007,

						/* registers */

	MasterAddress		= 0x0000,

	MasterLen		= 0x0006,

	MasterStatus		= 0x000C,

						/* MasterStatus bits */

	masterAbort		= 0x0001,

	targetAbort		= 0x0002,

	targetRetry		= 0x0004,

	targetDisc		= 0x0008,

	masterDownload		= 0x1000,

	masterUpload		= 0x4000,

	masterInProgress	= 0x8000,

	masterMask		= 0xD00F,

};

enum {						/* 3C90x extended register set */

	TIMER905		= 0x001A,	/* 8-bits */

	TxStatus905		= 0x001B,	/* 8-bits */

	PktStatus		= 0x0020,	/* 32-bits */

	DnListPtr		= 0x0024,	/* 32-bits, 8-byte aligned */

	FragAddr		= 0x0028,	/* 32-bits */

	FragLen			= 0x002C,	/* 16-bits */

	ListOffset		= 0x002E,	/* 8-bits */

	TxFreeThresh		= 0x002F,	/* 8-bits */

	UpPktStatus		= 0x0030,	/* 32-bits */

	FreeTIMER		= 0x0034,	/* 16-bits */

	UpListPtr		= 0x0038,	/* 32-bits, 8-byte aligned */

						/* PktStatus bits */

	fragLast		= 0x00000001,

	dnCmplReq		= 0x00000002,

	dnStalled		= 0x00000004,

	upCompleteX		= 0x00000008,

	dnCompleteX		= 0x00000010,

	upRxEarlyEnable		= 0x00000020,

	armCountdown		= 0x00000040,

	dnInProg		= 0x00000080,

	counterSpeed		= 0x00000010,	/* 0 3.2uS, 1 320nS */

	countdownMode		= 0x00000020,

						/* UpPktStatus bits (dpd->control) */

	upPktLenMask		= 0x00001FFF,

	upStalled		= 0x00002000,

	upError			= 0x00004000,

	upPktComplete		= 0x00008000,

	upOverrun		= 0x00010000,	/* RxError<<16 */

	upRuntFrame		= 0x00020000,

	upAlignmentError	= 0x00040000,

	upCRCError		= 0x00080000,

	upOversizedFrame	= 0x00100000,

	upDribbleBits		= 0x00800000,

	upOverflow		= 0x01000000,

	dnIndicate		= 0x80000000,	/* FrameStartHeader (dpd->control) */

	updnLastFrag		= 0x80000000,	/* (dpd->len) */

	Nup			= 32,

	Ndn			= 64,

};

/*

 * Up/Dn Packet Descriptors.

 * The hardware info (np, control, addr, len) must be 8-byte aligned

 * and this structure size must be a multiple of 8.

 */

typedef struct Pd Pd;

typedef struct Pd {

	ulong	np;			/* next pointer */

	ulong	control;		/* FSH or UpPktStatus */

	ulong	addr;

	ulong	len;

	Pd*	next;

	Block*	bp;

} Pd;

typedef struct Ctlr Ctlr;

typedef struct Ctlr {

	int	port;

	Pcidev*	pcidev;

	int	irq;

	Ctlr*	next;

	int	active;

	int	did;

	Lock	wlock;			/* window access */

	int	attached;

	int	busmaster;

	Block*	rbp;			/* receive buffer */

	Block*	txbp;			/* FIFO -based transmission */

	int	txthreshold;

	int	txbusy;

	int	nup;			/* full-busmaster -based reception */

	void*	upbase;

	Pd*	upr;

	Pd*	uphead;

	int	ndn;			/* full-busmaster -based transmission */

	void*	dnbase;

	Pd*	dnr;

	Pd*	dnhead;

	Pd*	dntail;

	int	dnq;

	long	interrupts;		/* statistics */

	long	bogusinterrupts;

	long	timer[2];

	long	stats[BytesRcvdOk+3];

	int	upqmax;

	int	upqmaxhw;

	ulong	upinterrupts;

	ulong	upqueued;

	ulong	upstalls;

	int	dnqmax;

	int	dnqmaxhw;

	ulong	dninterrupts;

	ulong	dnqueued;

	int	xcvr;			/* transceiver type */

	int	eepromcmd;		/* EEPROM read command */

	int	rxstatus9;		/* old-style RxStatus register */

	int	rxearly;		/* RxEarlyThreshold */

	int	ts;			/* threshold shift */

	int	upenabled;

	int	dnenabled;

	ulong	cbfnpa;			/* CardBus functions */

	ulong*	cbfn;

} Ctlr;

static Ctlr* ctlrhead;

static Ctlr* ctlrtail;

static void

init905(Ctlr* ctlr)

{

	Block *bp;

	Pd *pd, *prev;

	/*

	 * Create rings for the receive and transmit sides.

	 * Take care with alignment:

	 *	make sure ring base is 8-byte aligned;

	 *	make sure each entry is 8-byte aligned.

	 */

	ctlr->upbase = malloc((ctlr->nup+1)*sizeof(Pd));

	if(ctlr->upbase == nil)

		error(Enomem);

	ctlr->upr = (Pd*)ROUNDUP((ulong)ctlr->upbase, 8);

	prev = ctlr->upr;

	for(pd = &ctlr->upr[ctlr->nup-1]; pd >= ctlr->upr; pd--){

		pd->np = PADDR(&prev->np);

		pd->control = 0;

		bp = iallocb(sizeof(Etherpkt));

		if(bp == nil)

			panic("can't allocate ethernet receive ring");

		pd->addr = PADDR(bp->rp);

		pd->len = updnLastFrag|sizeof(Etherpkt);

		pd->next = prev;

		prev = pd;

		pd->bp = bp;

	}

	ctlr->uphead = ctlr->upr;

	ctlr->dnbase = malloc((ctlr->ndn+1)*sizeof(Pd));

	if(ctlr->dnbase == nil) {

		free(ctlr->upbase);

		error(Enomem);

	}

	ctlr->dnr = (Pd*)ROUNDUP((ulong)ctlr->dnbase, 8);

	prev = ctlr->dnr;

	for(pd = &ctlr->dnr[ctlr->ndn-1]; pd >= ctlr->dnr; pd--){

		pd->next = prev;

		prev = pd;

	}

	ctlr->dnhead = ctlr->dnr;

	ctlr->dntail = ctlr->dnr;

	ctlr->dnq = 0;

}

static Block*

rbpalloc(Block* (*f)(int))

{

	Block *bp;

	ulong addr;

	/*

	 * The receive buffers must be on a 32-byte

	 * boundary for EISA busmastering.

	 */

	if(bp = f(ROUNDUP(sizeof(Etherpkt), 4) + 31)){

		addr = (ulong)bp->base;

		addr = ROUNDUP(addr, 32);

		bp->rp = (uchar*)addr;

	}

	return bp;

}

static uchar*

startdma(Ether* ether, ulong address)

{

	int port, status, w;

	uchar *wp;

	port = ether->port;

	w = (STATUS(port)>>13) & 0x07;

	COMMAND(port, SelectRegisterWindow, Wmaster);

	wp = KADDR(inl(port+MasterAddress));

	status = ins(port+MasterStatus);

	if(status & (masterInProgress|targetAbort|masterAbort))

		print("#l%d: BM status 0x%uX\n", ether->ctlrno, status);

	outs(port+MasterStatus, masterMask);

	outl(port+MasterAddress, address);

	outs(port+MasterLen, sizeof(Etherpkt));

	COMMAND(port, StartDma, Upload);

	COMMAND(port, SelectRegisterWindow, w);

	return wp;

}

static void

promiscuous(void* arg, int on)

{

	int filter, port;

	Ether *ether;

	ether = (Ether*)arg;

	port = ether->port;

	filter = receiveBroadcast|receiveIndividual;

	if(ether->nmaddr)

		filter |= receiveMulticast;

	if(on)

		filter |= receiveAllFrames;

	COMMAND(port, SetRxFilter, filter);

}

static void

multicast(void* arg, uchar *addr, int on)

{

	int filter, port;

	Ether *ether;

	USED(addr, on);

	ether = (Ether*)arg;

	port = ether->port;

	filter = receiveBroadcast|receiveIndividual;

	if(ether->nmaddr)

		filter |= receiveMulticast;

	if(ether->prom)

		filter |= receiveAllFrames;

	COMMAND(port, SetRxFilter, filter);

}

/* On the 575B and C, interrupts need to be acknowledged in CardBus memory space */

static void

intrackcb(ulong *cbfn)

{

	cbfn[1] = 0x8000;

}

static void

attach(Ether* ether)

{

	int port, x;

	Ctlr *ctlr;

	ctlr = ether->ctlr;

	ilock(&ctlr->wlock);

	if(ctlr->attached){

		iunlock(&ctlr->wlock);

		return;

	}

	port = ether->port;

	/*

	 * Set the receiver packet filter for this and broadcast addresses,

	 * set the interrupt masks for all interrupts, enable the receiver

	 * and transmitter.

	 */

	promiscuous(ether, ether->prom);

	x = interruptMask;

	if(ctlr->busmaster == 1)

		x &= ~(rxEarly|rxComplete);

	else{

		if(ctlr->dnenabled)

			x &= ~transferInt;

		if(ctlr->upenabled)

			x &= ~(rxEarly|rxComplete);

	}

	COMMAND(port, SetIndicationEnable, x);

	COMMAND(port, SetInterruptEnable, x);

	COMMAND(port, RxEnable, 0);

	COMMAND(port, TxEnable, 0);

	/*

	 * If this is a CardBus card, acknowledge any interrupts.

	 */

	if(ctlr->cbfn != nil)

		intrackcb(ctlr->cbfn);

	/*

	 * Prime the busmaster channel for receiving directly into a

	 * receive packet buffer if necessary.

	 */

	if(ctlr->busmaster == 1)

		startdma(ether, PADDR(ctlr->rbp->rp));

	else{

		if(ctlr->upenabled)

			outl(port+UpListPtr, PADDR(&ctlr->uphead->np));

	}

	ctlr->attached = 1;

	iunlock(&ctlr->wlock);

}

static void

statistics(Ether* ether)

{

	int port, i, u, w;

	Ctlr *ctlr;

	port = ether->port;

	ctlr = ether->ctlr;

	/*

	 * 3C59[27] require a read between a PIO write and

	 * reading a statistics register.

	 */

	w = (STATUS(port)>>13) & 0x07;

	COMMAND(port, SelectRegisterWindow, Wstatistics);

	STATUS(port);

	for(i = 0; i < UpperFramesOk; i++)

		ctlr->stats[i] += inb(port+i) & 0xFF;

	u = inb(port+UpperFramesOk) & 0xFF;

	ctlr->stats[FramesXmittedOk] += (u & 0x30)<<4;

	ctlr->stats[FramesRcvdOk] += (u & 0x03)<<8;

	ctlr->stats[BytesRcvdOk] += ins(port+BytesRcvdOk) & 0xFFFF;

	ctlr->stats[BytesRcvdOk+1] += ins(port+BytesXmittedOk) & 0xFFFF;

	switch(ctlr->xcvr){

	case xcvrMii:

	case xcvr100BaseTX:

	case xcvr100BaseFX:

		COMMAND(port, SelectRegisterWindow, Wdiagnostic);

		STATUS(port);

		ctlr->stats[BytesRcvdOk+2] += inb(port+BadSSD);

		break;

	}

	COMMAND(port, SelectRegisterWindow, w);

}

static void

txstart(Ether* ether)

{

	int port, len;

	Ctlr *ctlr;

	Block *bp;

	port = ether->port;

	ctlr = ether->ctlr;

	/*

	 * Attempt to top-up the transmit FIFO. If there's room simply

	 * stuff in the packet length (unpadded to a dword boundary), the

	 * packet data (padded) and remove the packet from the queue.

	 * If there's no room post an interrupt for when there is.

	 * This routine is called both from the top level and from interrupt

	 * level and expects to be called with ctlr->wlock already locked

	 * and the correct register window (Wop) in place.

	 */

	for(;;){

		if(ctlr->txbp){

			bp = ctlr->txbp;

			ctlr->txbp = 0;

		}

		else{

			bp = qget(ether->oq);

			if(bp == nil)

				break;

		}

		len = ROUNDUP(BLEN(bp), 4);

		if(len+4 <= ins(port+TxFree)){

			outl(port+Fifo, BLEN(bp));

			outsl(port+Fifo, bp->rp, len/4);

			freeb(bp);

			ether->outpackets++;

		}

		else{

			ctlr->txbp = bp;

			if(ctlr->txbusy == 0){

				ctlr->txbusy = 1;

				COMMAND(port, SetTxAvailableThresh, len>>ctlr->ts);

			}

			break;

		}

	}

}

static void

txstart905(Ether* ether)

{

	Ctlr *ctlr;

	int port, stalled, timeo;

	Block *bp;

	Pd *pd;

	ctlr = ether->ctlr;

	port = ether->port;

	/*

	 * Free any completed packets.

	 */

	pd = ctlr->dntail;

	while(ctlr->dnq){

		if(PADDR(&pd->np) == inl(port+DnListPtr))

			break;

		if(pd->bp){

			freeb(pd->bp);

			pd->bp = nil;

		}

		ctlr->dnq--;

		pd = pd->next;

	}

	ctlr->dntail = pd;

	stalled = 0;

	while(ctlr->dnq < (ctlr->ndn-1)){

		bp = qget(ether->oq);

		if(bp == nil)

			break;

		pd = ctlr->dnhead->next;

		pd->np = 0;

		pd->control = dnIndicate|BLEN(bp);

		pd->addr = PADDR(bp->rp);

		pd->len = updnLastFrag|BLEN(bp);

		pd->bp = bp;

		if(stalled == 0 && ctlr->dnq && inl(port+DnListPtr)){

			COMMAND(port, Stall, dnStall);

			for(timeo = 100; (STATUS(port) & commandInProgress) && timeo; timeo--)

				;

			if(timeo == 0)

				print("#l%d: dnstall %d\n", ether->ctlrno, timeo);

			stalled = 1;

		}

		coherence();

		ctlr->dnhead->np = PADDR(&pd->np);

		ctlr->dnhead->control &= ~dnIndicate;

		ctlr->dnhead = pd;

		if(ctlr->dnq == 0)

			ctlr->dntail = pd;

		ctlr->dnq++;

		ctlr->dnqueued++;

	}

	if(ctlr->dnq > ctlr->dnqmax)

		ctlr->dnqmax = ctlr->dnq;

	/*

	 * If the adapter is not currently processing anything

	 * and there is something on the queue, start it processing.

	 */

	if(inl(port+DnListPtr) == 0 && ctlr->dnq)

		outl(port+DnListPtr, PADDR(&ctlr->dnhead->np));

	if(stalled)

		COMMAND(port, Stall, dnUnStall);

}

static void

transmit(Ether* ether)

{

	Ctlr *ctlr;

	int port, w;

	port = ether->port;

	ctlr = ether->ctlr;

	ilock(&ctlr->wlock);

	if(ctlr->dnenabled)

		txstart905(ether);

	else{

		w = (STATUS(port)>>13) & 0x07;

		COMMAND(port, SelectRegisterWindow, Wop);

		txstart(ether);

		COMMAND(port, SelectRegisterWindow, w);

	}

	iunlock(&ctlr->wlock);

}

static void

receive905(Ether* ether)

{

	Ctlr *ctlr;

	int len, port, q;

	Pd *pd;

	Block *bp;

	ctlr = ether->ctlr;

	port = ether->port;

	if(inl(port+UpPktStatus) & upStalled)

		ctlr->upstalls++;

	q = 0;

	for(pd = ctlr->uphead; pd->control & upPktComplete; pd = pd->next){

		if(pd->control & upError){

			if(pd->control & upOverrun)

				ether->overflows++;

			if(pd->control & (upOversizedFrame|upRuntFrame))

				ether->buffs++;

			if(pd->control & upAlignmentError)

				ether->frames++;

			if(pd->control & upCRCError)

				ether->crcs++;

		}

		else if(bp = iallocb(sizeof(Etherpkt)+4)){

			len = pd->control & rxBytes;

			pd->bp->wp = pd->bp->rp+len;

			etheriq(ether, pd->bp, 1);

			pd->bp = bp;

			pd->addr = PADDR(bp->rp);

			coherence();

		}

		pd->control = 0;

		COMMAND(port, Stall, upUnStall);

		q++;

	}

	ctlr->uphead = pd;

	ctlr->upqueued += q;

	if(q > ctlr->upqmax)

		ctlr->upqmax = q;

}

static void

receive(Ether* ether)

{

	int len, port, rxerror, rxstatus;

	Ctlr *ctlr;

	Block *bp;

	port = ether->port;

	ctlr = ether->ctlr;

	while(((rxstatus = ins(port+RxStatus)) & rxIncomplete) == 0){

		if(ctlr->busmaster == 1 && (STATUS(port) & busMasterInProgress))

			break;

		/*

		 * If there was an error, log it and continue.

		 * Unfortunately the 3C5[078]9 has the error info in the status register

		 * and the 3C59[0257] implement a separate RxError register.

		 */

		if(rxstatus & rxError){

			if(ctlr->rxstatus9){

				switch(rxstatus & rxError9){

				case rxOverrun9:

					ether->overflows++;

					break;

				case oversizedFrame9:

				case runtFrame9:

					ether->buffs++;

					break;

				case alignmentError9:

					ether->frames++;

					break;

				case crcError9:

					ether->crcs++;

					break;

				}

			}