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/*
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* on return from this function we will be running in virtual mode.
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* We set up the Block Address Translation (BAT) registers thus:
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* 1) first 3 BATs are 256M blocks, starting from KZERO->0
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* 2) remaining BAT maps last 256M directly
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*/
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TEXT mmuinit0(SB), $0
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/* reset all the tlbs */
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MOVW $64, R3
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10 |
MOVW R3, CTR
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MOVW $0, R4
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tlbloop:
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TLBIE R4
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14 |
SYNC
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ADD $BIT(19), R4
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BDNZ tlbloop
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TLBSYNC
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18 |
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19 |
/* BATs 0 and 1 cover memory from 0x00000000 to 0x20000000 */
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20 |
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/* KZERO -> 0, IBAT and DBAT, 256 MB */
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MOVW $(KZERO|(0x7ff<<2)|2), R3
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MOVW $(PTEVALID|PTEWRITE), R4 /* PTEVALID => Cache coherency on */
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MOVW R3, SPR(IBATU(0))
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MOVW R4, SPR(IBATL(0))
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MOVW R3, SPR(DBATU(0))
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MOVW R4, SPR(DBATL(0))
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28 |
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/* KZERO+256M -> 256M, IBAT and DBAT, 256 MB */
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ADD $(1<<28), R3
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ADD $(1<<28), R4
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MOVW R3, SPR(IBATU(1))
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MOVW R4, SPR(IBATL(1))
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MOVW R3, SPR(DBATU(1))
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MOVW R4, SPR(DBATL(1))
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36 |
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/* FPGABASE -> FPGABASE, DBAT, 16 MB */
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MOVW $(FPGABASE|(0x7f<<2)|2), R3
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MOVW $(FPGABASE|PTEWRITE|PTEUNCACHED), R4 /* FPGA memory, don't cache */
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MOVW R3, SPR(DBATU(2))
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MOVW R4, SPR(DBATL(2))
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/* IBAT 2 unused */
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MOVW R0, SPR(IBATU(2))
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MOVW R0, SPR(IBATL(2))
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46 |
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/* direct map last block, uncached, (not guarded, doesn't work for BAT), DBAT only */
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MOVW $(INTMEM|(0x7ff<<2)|2), R3
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MOVW $(INTMEM|PTEWRITE|PTEUNCACHED), R4 /* Don't set PTEVALID here */
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MOVW R3, SPR(DBATU(3))
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MOVW R4, SPR(DBATL(3))
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/* IBAT 3 unused */
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MOVW R0, SPR(IBATU(3))
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MOVW R0, SPR(IBATL(3))
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/* enable MMU */
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MOVW LR, R3
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OR $KZERO, R3
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MOVW R3, SPR(SRR0) /* Stored PC for RFI instruction */
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MOVW MSR, R4
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OR $(MSR_IR|MSR_DR|MSR_RI|MSR_FP), R4
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MOVW R4, SPR(SRR1)
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64 |
RFI /* resume in kernel mode in caller */
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65 |
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66 |
RETURN
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