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#include <u.h>
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#include <libc.h>
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#include <bio.h>
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#include "pci.h"
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#include "vga.h"
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/*
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 * Tvp3026 Viewpoint Video Interface Palette.
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 * Assumes hooked up to an S3 chip of some kind.
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 * Why is register access different from the
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 * Tvp302[05]?
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 */
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enum {
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	Index		= 0x00,		/* Index register */
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	Data		= 0x0A,		/* Data register */
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	Id		= 0x3F,		/* ID Register */
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	Tvp3026		= 0x26,
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};
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static uchar
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tvp3026io(uchar reg, uchar data)
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{
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	uchar crt55;
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	crt55 = vgaxi(Crtx, 0x55) & 0xFC;
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	vgaxo(Crtx, 0x55, crt55|((reg>>2) & 0x03));
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	vgao(dacxreg[reg & 0x03], data);
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	return crt55;
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}
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static uchar
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tvp3026i(uchar reg)
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{
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	uchar crt55, r;
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	crt55 = vgaxi(Crtx, 0x55) & 0xFC;
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	vgaxo(Crtx, 0x55, crt55|((reg>>2) & 0x03));
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	r = vgai(dacxreg[reg & 0x03]);
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	vgaxo(Crtx, 0x55, crt55);
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	return r;
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}
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uchar
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tvp3026xi(uchar index)
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{
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	uchar crt55, r;
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	crt55 = tvp3026io(Index, index);
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	vgaxo(Crtx, 0x55, crt55|((Data>>2) & 0x03));
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	r = vgai(dacxreg[Data & 0x03]);
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	vgaxo(Crtx, 0x55, crt55);
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	return r;
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}
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static void
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tvp3026o(uchar reg, uchar data)
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{
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	uchar crt55;
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	crt55 = tvp3026io(reg, data);
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	vgaxo(Crtx, 0x55, crt55);
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}
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void
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tvp3026xo(uchar index, uchar data)
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{
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	uchar crt55;
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	crt55 = tvp3026io(Index, index);
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	vgaxo(Crtx, 0x55, crt55|((Data>>2) & 0x03));
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	vgao(dacxreg[Data & 0x03], data);
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	vgaxo(Crtx, 0x55, crt55);
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}
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static void
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options(Vga*, Ctlr* ctlr)
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{
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	ctlr->flag |= Hclk2|Hextsid|Henhanced|Foptions;
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}
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static void
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init(Vga* vga, Ctlr* ctlr)
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{
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	ulong grade;
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	char *p;
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	/*
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	 * Work out the part speed-grade from name. Name can have,
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	 * e.g. '-135' on the end  for 135MHz part.
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	 */
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	grade = 110000000;
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	if(p = strrchr(ctlr->name, '-'))
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		grade = strtoul(p+1, 0, 0) * 1000000;
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	/*
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	 * If we don't already have a desired pclk,
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	 * take it from the mode.
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	 * Check it's within range.
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	 */
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	if(vga->f[0] == 0)
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		vga->f[0] = vga->mode->frequency;
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	if(vga->f[0] > grade)
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		error("%s: invalid pclk - %ld\n", ctlr->name, vga->f[0]);
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	/*
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	 * Determine whether to use clock-doubler or not.
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	 */
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	if((ctlr->flag & Uclk2) == 0 && vga->mode->z == 8 && vga->f[0] > 85000000)
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		resyncinit(vga, ctlr, Uclk2, 0);
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	ctlr->flag |= Finit;
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}
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static void
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load(Vga* vga, Ctlr* ctlr)
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{
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	uchar x;
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	/*
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	 * General Control:
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	 *	output sync polarity
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	 * It's important to set this properly and to turn off the
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	 * VGA controller H and V syncs. Can't be set in VGA mode.
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	 */
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	x = 0x00;
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	if((vga->misc & 0x40) == 0)
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		x |= 0x01;
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	if((vga->misc & 0x80) == 0)
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		x |= 0x02;
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	tvp3026xo(0x1D, x);
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	vga->misc |= 0xC0;
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	vgao(MiscW, vga->misc);
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	ctlr->flag |= Fload;
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}
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static void
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dump(Vga*, Ctlr* ctlr)
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{
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	int i;
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	ulong clock[4], f;
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	printitem(ctlr->name, "direct");
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	for(i = 0; i < 16; i++)
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		printreg(tvp3026i(i));
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	printitem(ctlr->name, "index");
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	for(i = 0; i < 64; i++)
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		printreg(tvp3026xi(i));
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	printitem(ctlr->name, "PCLK");
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	for(i = 0; i < 3; i++){
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		tvp3026xo(0x2C, (i<<4)|(i<<2)|i);
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		printreg(clock[i] = tvp3026xi(0x2D));
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	}
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	f = (RefFreq*(65-clock[1]))/(65-(clock[0] & 0x3F));
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	f >>= clock[2] & 0x03;
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	Bprint(&stdout, "%23ld", f);
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	printitem(ctlr->name, "MCLK");
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	for(i = 0; i < 3; i++){
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		tvp3026xo(0x2C, (i<<4)|(i<<2)|i);
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		printreg(clock[i] = tvp3026xi(0x2E));
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	}
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	f = (RefFreq*(65-clock[1]))/(65-(clock[0] & 0x3F));
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	f >>= clock[2] & 0x03;
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	Bprint(&stdout, "%23ld", f);
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174 
	printitem(ctlr->name, "LCLK");
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	for(i = 0; i < 3; i++){
176 
		tvp3026xo(0x2C, (i<<4)|(i<<2)|i);
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		printreg(clock[i] = tvp3026xi(0x2F));
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	}
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	Bprint(&stdout, "\n");
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}
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Ctlr tvp3026 = {
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	"tvp3026",			/* name */
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	0,				/* snarf */
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	options,			/* options */
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	init,				/* init */
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	0,				/* load */
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	dump,				/* dump */
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};