Subversion Repositories planix.SVN

Rev

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2 - 1 
#include	"l.h"
2 
 
3 
/* note: not finished
4 
 *	movd	fr,mem
5 
 *	movd	mem,fr
6 
 *	addv
7 
 *	addvu
8 
 *	subv
9 
 *	subvu
10 
 *	mulv
11 
 *	mulvu
12 
 *	divv
13 
 *	divvu
14 
 *	remv
15 
 *	remvu
16 
 */
17 
 
18 
#define	X	99
19 
 
20 
Optab	optab[] =
21 
{
22 
	{ ATEXT,	C_LEXT,	C_NONE,	C_LCON, 	 0, 0, 0 },
23 
	{ ATEXT,	C_LEXT,	C_REG,	C_LCON, 	 0, 0, 0 },
24 
 
25 
	{ AMOVW,	C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
26 
	{ AMOVV,	C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
27 
	{ AMOVB,	C_REG,	C_NONE,	C_REG,		12, 8, 0 },
28 
	{ AMOVBU,	C_REG,	C_NONE,	C_REG,		13, 4, 0 },
29 
 
30 
	{ ASUB,		C_REG,	C_REG,	C_REG,		 2, 4, 0 },
31 
	{ AADD,		C_REG,	C_REG,	C_REG,		 2, 4, 0 },
32 
	{ AAND,		C_REG,	C_REG,	C_REG,		 2, 4, 0 },
33 
	{ ASUB,		C_REG,	C_NONE,	C_REG,		 2, 4, 0 },
34 
	{ AADD,		C_REG,	C_NONE,	C_REG,		 2, 4, 0 },
35 
	{ AAND,		C_REG,	C_NONE,	C_REG,		 2, 4, 0 },
36 
 
37 
	{ ASLL,		C_REG,	C_NONE,	C_REG,		 9, 4, 0 },
38 
	{ ASLL,		C_REG,	C_REG,	C_REG,		 9, 4, 0 },
39 
 
40 
	{ AADDF,	C_FREG,	C_NONE,	C_FREG,		32, 4, 0 },
41 
	{ AADDF,	C_FREG,	C_REG,	C_FREG,		32, 4, 0 },
42 
	{ ACMPEQF,	C_FREG,	C_REG,	C_NONE,		32, 4, 0 },
43 
	{ AABSF,	C_FREG,	C_NONE,	C_FREG,		33, 4, 0 },
44 
	{ AMOVF,	C_FREG,	C_NONE,	C_FREG,		33, 4, 0 },
45 
	{ AMOVD,	C_FREG,	C_NONE,	C_FREG,		33, 4, 0 },
46 
 
47 
	{ AMOVW,	C_REG,	C_NONE,	C_SEXT,		 7, 4, REGSB },
48 
	{ AMOVV,	C_REG,	C_NONE,	C_SEXT,		 7, 4, REGSB },
49 
	{ AMOVB,	C_REG,	C_NONE,	C_SEXT,		 7, 4, REGSB },
50 
	{ AMOVBU,	C_REG,	C_NONE,	C_SEXT,		 7, 4, REGSB },
51 
	{ AMOVWL,	C_REG,	C_NONE,	C_SEXT,		 7, 4, REGSB },
52 
	{ AMOVW,	C_REG,	C_NONE,	C_SAUTO,	 7, 4, REGSP },
53 
	{ AMOVV,	C_REG,	C_NONE,	C_SAUTO,	 7, 4, REGSP },
54 
	{ AMOVB,	C_REG,	C_NONE,	C_SAUTO,	 7, 4, REGSP },
55 
	{ AMOVBU,	C_REG,	C_NONE,	C_SAUTO,	 7, 4, REGSP },
56 
	{ AMOVWL,	C_REG,	C_NONE,	C_SAUTO,	 7, 4, REGSP },
57 
	{ AMOVW,	C_REG,	C_NONE,	C_SOREG,	 7, 4, REGZERO },
58 
	{ AMOVV,	C_REG,	C_NONE,	C_SOREG,	 7, 4, REGZERO },
59 
	{ AMOVB,	C_REG,	C_NONE,	C_SOREG,	 7, 4, REGZERO },
60 
	{ AMOVBU,	C_REG,	C_NONE,	C_SOREG,	 7, 4, REGZERO },
61 
	{ AMOVWL,	C_REG,	C_NONE,	C_SOREG,	 7, 4, REGZERO },
62 
 
63 
	{ AMOVW,	C_SEXT,	C_NONE,	C_REG,		 8, 4, REGSB },
64 
	{ AMOVV,	C_SEXT,	C_NONE,	C_REG,		 8, 4, REGSB },
65 
	{ AMOVB,	C_SEXT,	C_NONE,	C_REG,		 8, 4, REGSB },
66 
	{ AMOVBU,	C_SEXT,	C_NONE,	C_REG,		 8, 4, REGSB },
67 
	{ AMOVWL,	C_SEXT,	C_NONE,	C_REG,		 8, 4, REGSB },
68 
	{ AMOVW,	C_SAUTO,C_NONE,	C_REG,		 8, 4, REGSP },
69 
	{ AMOVV,	C_SAUTO,C_NONE,	C_REG,		 8, 4, REGSP },
70 
	{ AMOVB,	C_SAUTO,C_NONE,	C_REG,		 8, 4, REGSP },
71 
	{ AMOVBU,	C_SAUTO,C_NONE,	C_REG,		 8, 4, REGSP },
72 
	{ AMOVWL,	C_SAUTO,C_NONE,	C_REG,		 8, 4, REGSP },
73 
	{ AMOVW,	C_SOREG,C_NONE,	C_REG,		 8, 4, REGZERO },
74 
	{ AMOVV,	C_SOREG,C_NONE,	C_REG,		 8, 4, REGZERO },
75 
	{ AMOVB,	C_SOREG,C_NONE,	C_REG,		 8, 4, REGZERO },
76 
	{ AMOVBU,	C_SOREG,C_NONE,	C_REG,		 8, 4, REGZERO },
77 
	{ AMOVWL,	C_SOREG,C_NONE,	C_REG,		 8, 4, REGZERO },
78 
 
79 
	{ AMOVW,	C_REG,	C_NONE,	C_LEXT,		35, 16, REGSB },
80 
	{ AMOVV,	C_REG,	C_NONE,	C_LEXT,		35, 16, REGSB },
81 
	{ AMOVB,	C_REG,	C_NONE,	C_LEXT,		35, 16, REGSB },
82 
	{ AMOVBU,	C_REG,	C_NONE,	C_LEXT,		35, 16, REGSB },
83 
	{ AMOVW,	C_REG,	C_NONE,	C_LAUTO,	35, 16, REGSP },
84 
	{ AMOVV,	C_REG,	C_NONE,	C_LAUTO,	35, 16, REGSP },
85 
	{ AMOVB,	C_REG,	C_NONE,	C_LAUTO,	35, 16, REGSP },
86 
	{ AMOVBU,	C_REG,	C_NONE,	C_LAUTO,	35, 16, REGSP },
87 
	{ AMOVW,	C_REG,	C_NONE,	C_LOREG,	35, 16, REGZERO },
88 
	{ AMOVV,	C_REG,	C_NONE,	C_LOREG,	35, 16, REGZERO },
89 
	{ AMOVB,	C_REG,	C_NONE,	C_LOREG,	35, 16, REGZERO },
90 
	{ AMOVBU,	C_REG,	C_NONE,	C_LOREG,	35, 16, REGZERO },
91 
 
92 
	{ AMOVW,	C_LEXT,	C_NONE,	C_REG,		36, 16, REGSB },
93 
	{ AMOVV,	C_LEXT,	C_NONE,	C_REG,		36, 16, REGSB },
94 
	{ AMOVB,	C_LEXT,	C_NONE,	C_REG,		36, 16, REGSB },
95 
	{ AMOVBU,	C_LEXT,	C_NONE,	C_REG,		36, 16, REGSB },
96 
	{ AMOVW,	C_LAUTO,C_NONE,	C_REG,		36, 16, REGSP },
97 
	{ AMOVV,	C_LAUTO,C_NONE,	C_REG,		36, 16, REGSP },
98 
	{ AMOVB,	C_LAUTO,C_NONE,	C_REG,		36, 16, REGSP },
99 
	{ AMOVBU,	C_LAUTO,C_NONE,	C_REG,		36, 16, REGSP },
100 
	{ AMOVW,	C_LOREG,C_NONE,	C_REG,		36, 16, REGZERO },
101 
	{ AMOVV,	C_LOREG,C_NONE,	C_REG,		36, 16, REGZERO },
102 
	{ AMOVB,	C_LOREG,C_NONE,	C_REG,		36, 16, REGZERO },
103 
	{ AMOVBU,	C_LOREG,C_NONE,	C_REG,		36, 16, REGZERO },
104 
 
105 
	{ AMOVW,	C_SECON,C_NONE,	C_REG,		 3, 4, REGSB },
106 
	{ AMOVW,	C_SACON,C_NONE,	C_REG,		 3, 4, REGSP },
107 
	{ AMOVW,	C_LECON,C_NONE,	C_REG,		26, 12, REGSB },
108 
	{ AMOVW,	C_LACON,C_NONE,	C_REG,		26, 12, REGSP },
109 
	{ AMOVW,	C_ADDCON,C_NONE,C_REG,		 3, 4, REGZERO },
110 
	{ AMOVW,	C_ANDCON,C_NONE,C_REG,		 3, 4, REGZERO },
111 
 
112 
	{ AMOVW,	C_UCON, C_NONE, C_REG,		24, 4, 0 },
113 
	{ AMOVW,	C_LCON,	C_NONE,	C_REG,		19, 8, 0 },
114 
 
115 
	{ AMOVW,	C_HI,	C_NONE,	C_REG,		20, 4, 0 },
116 
	{ AMOVV,	C_HI,	C_NONE,	C_REG,		20, 4, 0 },
117 
	{ AMOVW,	C_LO,	C_NONE,	C_REG,		20, 4, 0 },
118 
	{ AMOVV,	C_LO,	C_NONE,	C_REG,		20, 4, 0 },
119 
	{ AMOVW,	C_REG,	C_NONE,	C_HI,		21, 4, 0 },
120 
	{ AMOVV,	C_REG,	C_NONE,	C_HI,		21, 4, 0 },
121 
	{ AMOVW,	C_REG,	C_NONE,	C_LO,		21, 4, 0 },
122 
	{ AMOVV,	C_REG,	C_NONE,	C_LO,		21, 4, 0 },
123 
 
124 
	{ AMUL,		C_REG,	C_REG,	C_NONE,		22, 4, 0 },
125 
 
126 
	{ AADD,		C_ADD0CON,C_REG,C_REG,		 4, 4, 0 },
127 
	{ AADD,		C_ADD0CON,C_NONE,C_REG,		 4, 4, 0 },
128 
	{ AADD,		C_ANDCON,C_REG,	C_REG,		10, 8, 0 },
129 
	{ AADD,		C_ANDCON,C_NONE,C_REG,		10, 8, 0 },
130 
 
131 
	{ AAND,		C_AND0CON,C_REG,C_REG,		 4, 4, 0 },
132 
	{ AAND,		C_AND0CON,C_NONE,C_REG,		 4, 4, 0 },
133 
	{ AAND,		C_ADDCON,C_REG,	C_REG,		10, 8, 0 },
134 
	{ AAND,		C_ADDCON,C_NONE,C_REG,		10, 8, 0 },
135 
 
136 
	{ AADD,		C_UCON,	C_REG,	C_REG,		25, 8, 0 },
137 
	{ AADD,		C_UCON,	C_NONE,	C_REG,		25, 8, 0 },
138 
	{ AAND,		C_UCON,	C_REG,	C_REG,		25, 8, 0 },
139 
	{ AAND,		C_UCON,	C_NONE,	C_REG,		25, 8, 0 },
140 
 
141 
	{ AADD,		C_LCON,	C_NONE,	C_REG,		23, 12, 0 },
142 
	{ AAND,		C_LCON,	C_NONE,	C_REG,		23, 12, 0 },
143 
	{ AADD,		C_LCON,	C_REG,	C_REG,		23, 12, 0 },
144 
	{ AAND,		C_LCON,	C_REG,	C_REG,		23, 12, 0 },
145 
 
146 
	{ ASLL,		C_SCON,	C_REG,	C_REG,		16, 4, 0 },
147 
	{ ASLL,		C_SCON,	C_NONE,	C_REG,		16, 4, 0 },
148 
 
149 
	{ ASYSCALL,	C_NONE,	C_NONE,	C_NONE,		 5, 4, 0 },
150 
 
151 
	{ ABEQ,		C_REG,	C_REG,	C_SBRA,		 6, 4, 0 },
152 
	{ ABEQ,		C_REG,	C_NONE,	C_SBRA,		 6, 4, 0 },
153 
	{ ABLEZ,	C_REG,	C_NONE,	C_SBRA,		 6, 4, 0 },
154 
	{ ABFPT,	C_NONE,	C_NONE,	C_SBRA,		 6, 4, 0 },
155 
 
156 
	{ AJMP,		C_NONE,	C_NONE,	C_LBRA,		11, 4, 0 },
157 
	{ AJAL,		C_NONE,	C_NONE,	C_LBRA,		11, 4, 0 },
158 
 
159 
	{ AJMP,		C_NONE,	C_NONE,	C_ZOREG,	18, 4, REGZERO },
160 
	{ AJAL,		C_NONE,	C_NONE,	C_ZOREG,	18, 4, REGLINK },
161 
 
162 
	{ AMOVW,	C_SEXT,	C_NONE,	C_FREG,		27, 4, REGSB },
163 
	{ AMOVF,	C_SEXT,	C_NONE,	C_FREG,		27, 4, REGSB },
164 
	{ AMOVD,	C_SEXT,	C_NONE,	C_FREG,		27, 8, REGSB },
165 
	{ AMOVW,	C_SAUTO,C_NONE,	C_FREG,		27, 4, REGSP },
166 
	{ AMOVF,	C_SAUTO,C_NONE,	C_FREG,		27, 4, REGSP },
167 
	{ AMOVD,	C_SAUTO,C_NONE,	C_FREG,		27, 8, REGSP },
168 
	{ AMOVW,	C_SOREG,C_NONE,	C_FREG,		27, 4, REGZERO },
169 
	{ AMOVF,	C_SOREG,C_NONE,	C_FREG,		27, 4, REGZERO },
170 
	{ AMOVD,	C_SOREG,C_NONE,	C_FREG,		27, 8, REGZERO },
171 
 
172 
	{ AMOVW,	C_LEXT,	C_NONE,	C_FREG,		27, 16, REGSB },
173 
	{ AMOVF,	C_LEXT,	C_NONE,	C_FREG,		27, 16, REGSB },
174 
	{ AMOVD,	C_LEXT,	C_NONE,	C_FREG,		27, 20, REGSB },
175 
	{ AMOVW,	C_LAUTO,C_NONE,	C_FREG,		27, 16, REGSP },
176 
	{ AMOVF,	C_LAUTO,C_NONE,	C_FREG,		27, 16, REGSP },
177 
	{ AMOVD,	C_LAUTO,C_NONE,	C_FREG,		27, 20, REGSP },
178 
	{ AMOVW,	C_LOREG,C_NONE,	C_FREG,		27, 16, REGZERO },
179 
	{ AMOVF,	C_LOREG,C_NONE,	C_FREG,		27, 16, REGZERO },
180 
	{ AMOVD,	C_LOREG,C_NONE,	C_FREG,		27, 20, REGZERO },
181 
 
182 
	{ AMOVW,	C_FREG,	C_NONE,	C_SEXT,		28, 4, REGSB },
183 
	{ AMOVF,	C_FREG,	C_NONE,	C_SEXT,		28, 4, REGSB },
184 
	{ AMOVD,	C_FREG,	C_NONE,	C_SEXT,		28, 8, REGSB },
185 
	{ AMOVW,	C_FREG,	C_NONE,	C_SAUTO,	28, 4, REGSP },
186 
	{ AMOVF,	C_FREG,	C_NONE,	C_SAUTO,	28, 4, REGSP },
187 
	{ AMOVD,	C_FREG,	C_NONE,	C_SAUTO,	28, 8, REGSP },
188 
	{ AMOVW,	C_FREG,	C_NONE,	C_SOREG,	28, 4, REGZERO },
189 
	{ AMOVF,	C_FREG,	C_NONE,	C_SOREG,	28, 4, REGZERO },
190 
	{ AMOVD,	C_FREG,	C_NONE,	C_SOREG,	28, 8, REGZERO },
191 
 
192 
	{ AMOVW,	C_FREG,	C_NONE,	C_LEXT,		28, 16, REGSB },
193 
	{ AMOVF,	C_FREG,	C_NONE,	C_LEXT,		28, 16, REGSB },
194 
	{ AMOVD,	C_FREG,	C_NONE,	C_LEXT,		28, 20, REGSB },
195 
	{ AMOVW,	C_FREG,	C_NONE,	C_LAUTO,	28, 16, REGSP },
196 
	{ AMOVF,	C_FREG,	C_NONE,	C_LAUTO,	28, 16, REGSP },
197 
	{ AMOVD,	C_FREG,	C_NONE,	C_LAUTO,	28, 20, REGSP },
198 
	{ AMOVW,	C_FREG,	C_NONE,	C_LOREG,	28, 16, REGZERO },
199 
	{ AMOVF,	C_FREG,	C_NONE,	C_LOREG,	28, 16, REGZERO },
200 
	{ AMOVD,	C_FREG,	C_NONE,	C_LOREG,	28, 20, REGZERO },
201 
 
202 
	{ AMOVW,	C_REG,	C_NONE,	C_FREG,		30, 4, 0 },
203 
	{ AMOVW,	C_FREG,	C_NONE,	C_REG,		31, 4, 0 },
204 
 
205 
	{ AMOVW,	C_ADDCON,C_NONE,C_FREG,		34, 8, 0 },
206 
	{ AMOVW,	C_ANDCON,C_NONE,C_FREG,		34, 8, 0 },
207 
	{ AMOVW,	C_UCON, C_NONE, C_FREG,		35, 8, 0 },
208 
	{ AMOVW,	C_LCON,	C_NONE,	C_FREG,		36, 12, 0 },
209 
 
210 
	{ AMOVW,	C_REG,	C_NONE,	C_MREG,		37, 4, 0 },
211 
	{ AMOVV,	C_REG,	C_NONE,	C_MREG,		37, 4, 0 },
212 
	{ AMOVW,	C_MREG,	C_NONE,	C_REG,		38, 4, 0 },
213 
	{ AMOVV,	C_MREG,	C_NONE,	C_REG,		38, 4, 0 },
214 
 
215 
	{ ARFE,		C_NONE,	C_NONE,	C_ZOREG,	39, 8, 0 },
216 
	{ AWORD,	C_NONE,	C_NONE,	C_LCON,		40, 4, 0 },
217 
 
218 
	{ AMOVW,	C_REG,	C_NONE,	C_FCREG,	41, 8, 0 },
219 
	{ AMOVV,	C_REG,	C_NONE,	C_FCREG,	41, 8, 0 },
220 
	{ AMOVW,	C_FCREG,C_NONE,	C_REG,		42, 4, 0 },
221 
	{ AMOVV,	C_FCREG,C_NONE,	C_REG,		42, 4, 0 },
222 
 
223 
	{ ABREAK,	C_REG,	C_NONE,	C_SEXT,		 7, 4, REGSB },	/* really CACHE instruction */
224 
	{ ABREAK,	C_REG,	C_NONE,	C_SAUTO,	 7, 4, REGSP },
225 
	{ ABREAK,	C_REG,	C_NONE,	C_SOREG,	 7, 4, REGZERO },
226 
	{ ABREAK,	C_NONE,	C_NONE,	C_NONE,		 5, 4, 0 },
227 
 
228 
	{ ACASE,	C_REG,	C_NONE,	C_NONE,		 45, 28, 0 },
229 
	{ ABCASE,	C_LCON,	C_NONE,	C_LBRA,		 46, 4, 0 },
230 
 
231 
	{ AXXX,		C_NONE,	C_NONE,	C_NONE,		 0, 4, 0 },
232 
};