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Rev Author Line No. Line
2 - 1 
TEXT	ainc(SB),$0	/* long ainc(long *); */
2 
	MOVW	R3, R4
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xincloop:
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	LWAR	(R4), R3
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	ADD	$1, R3
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	DCBT	(R4)				/* fix 405 errata cpu_210 */
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	STWCCC	R3, (R4)
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	BNE	xincloop
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	RETURN
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11 
TEXT	adec(SB),$0	/* long adec(long *); */
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	MOVW	R3, R4
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xdecloop:
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	LWAR	(R4), R3
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	ADD	$-1, R3
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	DCBT	(R4)				/* fix 405 errata cpu_210 */
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	STWCCC	R3, (R4)
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	BNE	xdecloop
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	RETURN
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TEXT	loadlink(SB), $0
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	LWAR	(R3), R3
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	RETURN
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26 
TEXT	storecond(SB), $0
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	MOVW	val+4(FP), R4
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	DCBT	(R3)				/* fix 405 errata cpu_210 */
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	STWCCC	R4, (R3)
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	BNE	storecondfail
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	MOVW	$1, R3
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	RETURN
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storecondfail:
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	MOVW	$0, R3
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	RETURN
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38 
/*
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 * int cas32(u32int *p, u32int ov, u32int nv);
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 * int cas(uint *p, int ov, int nv);
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 * int casp(void **p, void *ov, void *nv);
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 * int casl(ulong *p, ulong ov, ulong nv);
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 */
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TEXT	cas32+0(SB),0,$0
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TEXT	cas+0(SB),0,$0
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TEXT	casp+0(SB),0,$0
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TEXT	casl+0(SB),0,$0
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	MOVW	ov+4(FP),R4
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	MOVW	nv+8(FP),R8
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	LWAR	(R3),R5
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	CMP	R5,R4
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	BNE	fail
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	DCBT	(R3)				/* fix 405 errata cpu_210 */
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	STWCCC	R8,(R3)
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	BNE	fail1
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	MOVW	$1,R3
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	RETURN
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fail:
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	DCBT	(R3)				/* fix 405 errata cpu_210 */
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	STWCCC	R5,(R3)	/* give up exclusive access */
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fail1:
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	MOVW	R0,R3
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	RETURN
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	END