Subversion Repositories planix.SVN

// Power PC support

defn acidinit()                 // Called after all the init modules are loaded
{
        bplist = {};
        bpfmt = 'X';

        srcpath = {
                "./",
                "/sys/src/libc/port/",
                "/sys/src/libc/9sys/",
                "/sys/src/libc/power/"
        };

        srcfiles = {};          // list of loaded files
        srctext = {};           // the text of the files
}

defn stk()                      // trace
{
        _stk(*PC, *SP, linkreg(0), 0);
}

defn lstk()                     // trace with locals
{
        _stk(*PC, *SP, linkreg(0), 1);
}

defn gpr()                      // print general purpose registers
{
        print("SP\t", *SP, " R2\t", *R2, " R3\t", *R3, "\n");
        print("R4\t", *R4, " R5\t", *R5, " R6\t", *R6, "\n");
        print("R7\t", *R7, " R8\t", *R8, " R9\t", *R9, "\n");
        print("R10\t", *R10, " R11\t", *R11, " R12\t", *R12, "\n");
        print("R13\t", *R13, " R14\t", *R14, " R15\t", *R15, "\n");
        print("R16\t", *R16, " R17\t", *R17, " R18\t", *R18, "\n");
        print("R19\t", *R19, " R20\t", *R20, " R21\t", *R21, "\n");
        print("R22\t", *R22, " R23\t", *R23, " R24\t", *R24, "\n");
        print("R25\t", *R25, " R26\t", *R26, " R27\t", *R27, "\n");
        print("R28\t", *R28, " R29\t", *R29, " R30\t", *R30, "\n");
        print("R31\t", *R31, "\n");
}

defn Fpr()
{
        fpr();
}

defn fpr()
{
        print("F0\t",  *fmt(F0, 'G'),  "\tF1\t",  *fmt(F1, 'G'), "\n");
        print("F2\t",  *fmt(F2, 'G'),  "\tF3\t",  *fmt(F3, 'G'), "\n");
        print("F4\t",  *fmt(F4, 'G'),  "\tF5\t",  *fmt(F5, 'G'), "\n");
        print("F6\t",  *fmt(F6, 'G'),  "\tF7\t",  *fmt(F7, 'G'), "\n");
        print("F8\t",  *fmt(F8, 'G'),  "\tF9\t",  *fmt(F9, 'G'), "\n");
        print("F10\t", *fmt(F10, 'G'), "\tF11\t", *fmt(F11, 'G'), "\n");
        print("F12\t", *fmt(F12, 'G'), "\tF13\t", *fmt(F13, 'G'), "\n");
        print("F14\t", *fmt(F14, 'G'), "\tF15\t", *fmt(F15, 'G'), "\n");
        print("F16\t", *fmt(F16, 'G'), "\tF17\t", *fmt(F17, 'G'), "\n");
        print("F18\t", *fmt(F18, 'G'), "\tF19\t", *fmt(F19, 'G'), "\n");
        print("F20\t", *fmt(F20, 'G'), "\tF21\t", *fmt(F21, 'G'), "\n");
        print("F22\t", *fmt(F22, 'G'), "\tF23\t", *fmt(F23, 'G'), "\n");
        print("F24\t", *fmt(F24, 'G'), "\tF25\t", *fmt(F25, 'G'), "\n");
        print("F26\t", *fmt(F26, 'G'), "\tF27\t", *fmt(F27, 'G'), "\n");
        print("F28\t", *fmt(F28, 'G'), "\tF29\t", *fmt(F29, 'G'), "\n");
        print("F30\t", *fmt(F30, 'G'), "\tF31\t", *fmt(F31, 'G'), "\n");
}

defn spr()                              // print special processor registers
{
        local pc, link, cause;

        pc = *PC;
        print("PC\t", pc, " ", fmt(pc, 'a'), "  ");
        pfl(pc);

        link = *R31;
        print("SP\t", *SP, "\tLINK\t", link, " ", fmt(link, 'a'), " ");
        pfl(link);

        cause = *CAUSE;
        print("SRR1\t", *SRR1, "\tCAUSE\t", cause, " ", reason(cause), "\n");
        print("LR\t", *LR, "\tCR\t", *CR, "\n");

        print("XER\t", *XER, "\tCTR\t", *CTR, "\n");
}

defn regs()                             // print all registers
{
        spr();
        gpr();
}

defn pstop(pid)
{
        local l, pc;

        pc = *PC;

        print(pid,": ", reason(*CAUSE), "\t");
        print(fmt(pc, 'a'), "\t", fmt(pc, 'i'), "\n");

        if notes then {
                if notes[0] != "sys: breakpoint" then {
                        print("Notes pending:\n");
                        l = notes;
                        while l do {
                                print("\t", head l, "\n");
                                l = tail l;
                        }
                }
        }
}

defn linkreg(addr)
{
        return *LR;
}

print("/sys/lib/acid/power");